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Commit 78d6cd5f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "Revert "ARM: dts: msm: Clean-up vidc DT node""

parents 7b01ccb4 b55a6ef7

qcom/lahaina-vidc.dtsi

+12 −12
Original line number Diff line number Diff line 
&soc {

	msm_vidc: vidc@aa00000 {

		compatible = "msm-vidc", "lahaina-vidc";

		status = "disabled";

	msm_vidc: qcom,vidc@aa00000 {

		compatible = "qcom,msm-vidc", "qcom,lahaina-vidc";

		status = "okay";

		reg = <0x0aa00000 0x00100000>;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
@@ -22,17 +22,17 @@ 
		clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,

			<&clock_videocc VIDEO_CC_MVS0C_CLK>,

			<&clock_videocc VIDEO_CC_MVS0_CLK>;

		vidc,proxy-clock-names = "gcc_video_axi0",

		qcom,proxy-clock-names = "gcc_video_axi0",

			"core_clk", "vcodec_clk";

		/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/

		vidc,clock-configs = <0x0 0x1 0x1>;

		vidc,allowed-clock-rates = <239999999 338000000

		qcom,clock-configs = <0x0 0x1 0x1>;

		qcom,allowed-clock-rates = <239999999 338000000

			366000000 444000000>;

		resets = <&clock_gcc GCC_VIDEO_AXI0_CLK_ARES>,

			<&clock_videocc VIDEO_CC_MVS0C_CLK_ARES>;

		reset-names = "video_axi_reset", "video_core_reset";



		vidc,reg-presets = <0xB0088 0x0 0x11>;

		qcom,reg-presets = <0xB0088 0x0 0x11>;



		/* Bus Interconnects */

		interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc";
@@ -43,13 +43,13 @@ 
				<&mmss_noc MASTER_VIDEO_P0

					&gem_noc SLAVE_LLCC>;

		/* Bus BW range (low, high) for each bus */

		vidc,bus-range-kbps = <1000 1000

		qcom,bus-range-kbps = <1000 1000

					1000 15000000

					1000 15000000>;



		/* MMUs */

		non_secure_cb {

			compatible = "msm-vidc-context-bank";

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_ns";

			iommus = <&apps_smmu 0x2100 0x0400>;

			qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
@@ -60,7 +60,7 @@ 
		};



		secure_non_pixel_cb {

			compatible = "msm-vidc-context-bank";

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_non_pixel";

			iommus = <&apps_smmu 0x2104 0x0400>;

			qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
@@ -73,7 +73,7 @@ 
		};



		secure_bitstream_cb {

			compatible = "msm-vidc-context-bank";

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_bitstream";

			iommus = <&apps_smmu 0x2101 0x0404>;

			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
@@ -86,7 +86,7 @@ 
		};



		secure_pixel_cb {

			compatible = "msm-vidc-context-bank";

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_pixel";

			iommus = <&apps_smmu 0x2103 0x0400>;

			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;