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Commit 789070f1 authored by Elaine Zhang's avatar Elaine Zhang Committed by Greg Kroah-Hartman
Browse files

ARM: dts: rockchip: Fix power-controller node names for rk3288 



[ Upstream commit 970cdc53cb1afa73602028c103dbfb6a230080be ]

Use more generic names (as recommended in the device tree specification
or the binding documentation)

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: default avatarEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: default avatarJohan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210417112952.8516-4-jbx6244@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 6aaffe6c

arch/arm/boot/dts/rk3288.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -771,7 +771,7 @@ 
			 *	*_HDMI		HDMI

			 *	*_MIPI_*	MIPI

			 */

			pd_vio@RK3288_PD_VIO {

			power-domain@RK3288_PD_VIO {

				reg = <RK3288_PD_VIO>;

				clocks = <&cru ACLK_IEP>,

					 <&cru ACLK_ISP>,
@@ -813,7 +813,7 @@ 
			 * Note: The following 3 are HEVC(H.265) clocks,

			 * and on the ACLK_HEVC_NIU (NOC).

			 */

			pd_hevc@RK3288_PD_HEVC {

			power-domain@RK3288_PD_HEVC {

				reg = <RK3288_PD_HEVC>;

				clocks = <&cru ACLK_HEVC>,

					 <&cru SCLK_HEVC_CABAC>,
@@ -827,7 +827,7 @@ 
			 * (video endecoder & decoder) clocks that on the

			 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).

			 */

			pd_video@RK3288_PD_VIDEO {

			power-domain@RK3288_PD_VIDEO {

				reg = <RK3288_PD_VIDEO>;

				clocks = <&cru ACLK_VCODEC>,

					 <&cru HCLK_VCODEC>;
@@ -838,7 +838,7 @@ 
			 * Note: ACLK_GPU is the GPU clock,

			 * and on the ACLK_GPU_NIU (NOC).

			 */

			pd_gpu@RK3288_PD_GPU {

			power-domain@RK3288_PD_GPU {

				reg = <RK3288_PD_GPU>;

				clocks = <&cru ACLK_GPU>;

				pm_qos = <&qos_gpu_r>,