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Commit 788e2f8e authored by Pratham Pratap's avatar Pratham Pratap Committed by Gerrit - the friendly Code Review server
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usb: dwc3: Set FORCE_MEM_CORE_ON bit of GCC_USB30_MASTER_CLK 



USB FORCE_MEM_CORE_ON retains the USB controller CSR when system
goes into and comes out from CXPC (i.e. using MX instead of CX).
This change sets the FORCE_MEM_CORE_ON bit of GCC_USB30_MASTER_CLK
by calling qcom_clk_set_flags API exposed by clock driver.

Change-Id: Ifb83b1b02214b034be53d2b443ae101688b4a97e
Signed-off-by: default avatarPratham Pratap <prathampratap@codeaurora.org>
parent 49eed0fd

drivers/usb/dwc3/dwc3-msm.c

+3 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/iommu.h>

#include <linux/ioport.h>

#include <linux/clk.h>

#include <linux/clk/qcom.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/types.h>
@@ -2187,6 +2188,7 @@ static int dwc3_msm_config_gdsc(struct dwc3_msm *mdwc, int on) 
			return ret;

		}



		qcom_clk_set_flags(mdwc->core_clk, CLKFLAG_RETAIN_MEM);

		ret = clk_prepare_enable(mdwc->core_csr_clk);

		if (ret) {

			regulator_disable(mdwc->dwc3_gdsc);
@@ -2194,6 +2196,7 @@ static int dwc3_msm_config_gdsc(struct dwc3_msm *mdwc, int on) 
			return ret;

		}

	} else {

		qcom_clk_set_flags(mdwc->core_clk, CLKFLAG_NORETAIN_MEM);

		clk_disable_unprepare(mdwc->core_csr_clk);

		ret = regulator_disable(mdwc->dwc3_gdsc);

		if (ret) {