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Commit 78864760 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: support sdma clock gating for more instances 



Shorten the code with RREG32_SDMA/WREG32_SDMA macro in CG part.

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5d111f5b

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+34 −71
Original line number Diff line number Diff line
@@ -2086,10 +2086,11 @@ static void sdma_v4_0_update_medium_grain_clock_gating( 
		bool enable)

{

	uint32_t data, def;

	int i;



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {

		/* enable sdma0 clock gating */

		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));

		for (i = 0; i < adev->sdma.num_instances; i++) {

			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);

			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |

				  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |

				  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
@@ -2099,24 +2100,11 @@ static void sdma_v4_0_update_medium_grain_clock_gating( 
				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |

				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);

			if (def != data)

			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);



		if (adev->sdma.num_instances > 1) {

			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));

			data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |

				  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |

				  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |

				  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |

				  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |

				  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |

				  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |

				  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);

			if (def != data)

				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);

				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);

		}

	} else {

		/* disable sdma0 clock gating */

		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));

		for (i = 0; i < adev->sdma.num_instances; i++) {

			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);

			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |

				 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |

				 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
@@ -2125,22 +2113,8 @@ static void sdma_v4_0_update_medium_grain_clock_gating( 
				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |

				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |

				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);



			if (def != data)

			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);



		if (adev->sdma.num_instances > 1) {

			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));

			data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |

				 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |

				 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |

				 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |

				 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |

				 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |

				 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |

				 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);

			if (def != data)

				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);

				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);

		}

	}

}
@@ -2151,34 +2125,23 @@ static void sdma_v4_0_update_medium_grain_light_sleep( 
		bool enable)

{

	uint32_t data, def;

	int i;



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {

		/* 1-not override: enable sdma0 mem light sleep */

		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

		for (i = 0; i < adev->sdma.num_instances; i++) {

			/* 1-not override: enable sdma mem light sleep */

			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);

			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;

			if (def != data)

			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);



		/* 1-not override: enable sdma1 mem light sleep */

		if (adev->sdma.num_instances > 1) {

			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));

			data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;

			if (def != data)

				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);

				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);

		}

	} else {

		/* 0-override:disable sdma0 mem light sleep */

		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

		for (i = 0; i < adev->sdma.num_instances; i++) {

		/* 0-override:disable sdma mem light sleep */

			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);

			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;

			if (def != data)

			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);



		/* 0-override:disable sdma1 mem light sleep */

		if (adev->sdma.num_instances > 1) {

			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));

			data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;

			if (def != data)

				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);

				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);

		}

	}

}