Merge tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Actions Semi S900 Pin Controller

This binding describes the pin controller found in the S900 SoC.

Required Properties:

- compatible:   Should be "actions,s900-pinctrl"

- reg:          Should contain the register base address and size of

                the pin controller.

- clocks:       phandle of the clock feeding the pin controller

Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.

PIN CONFIGURATION NODES:

The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.

Pinmux functions are available only for the pin groups while pinconf

parameters are available for both pin groups and individual pins.

The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:

Required Properties:

- pins:           An array of strings, each string containing the name of a pin.

                  These pins are used for selecting the pull control and schmitt

                  trigger parameters. The following are the list of pins

                  available:

                  eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv,

                  eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio,

                  sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0,

                  i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,

                  pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5,

                  eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,

                  lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,

                  lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan,

                  lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,

                  lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean,

                  sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1,

                  sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,

                  spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,

                  uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb,

                  uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx,

                  uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata,

                  i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1,

                  csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3,

                  csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,

                  dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,

                  csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,

                  sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3,

                  nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs,

                  nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1,

                  nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2,

                  nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs,

                  nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1,

                  nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3

- groups:         An array of strings, each string containing the name of a pin

                  group. These pin groups are used for selecting the pinmux

                  functions.

                  lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,

                  sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,

                  rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,

                  rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,

                  i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp,

                  pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp,

                  eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp,

                  eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp,

                  lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp,

                  spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,

                  uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,

                  sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp,

                  uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp,

                  csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp,

                  dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,

                  nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,

                  csi1_dn0_dp0_mfp, uart4_rx_tx_mfp

                  These pin groups are used for selecting the drive strength

                  parameters.

                  sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv,

                  rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv,

                  rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv,

                  sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv,

                  i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv,

                  lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv,

                  sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv,

                  spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv,

                  uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv

                  These pin groups are used for selecting the slew rate

                  parameters.

                  sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,

                  rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,

                  rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,

                  i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,

                  pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,

                  spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,

                  uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,

                  sensor0_sr

- function:       An array of strings, each string containing the name of the

                  pinmux functions. These functions can only be selected by

                  the corresponding pin groups. The following are the list of

                  pinmux functions available:

                  eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,

                  uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,

                  pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,

                  sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,

                  usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,

                  nand1, spdif, sirq0, sirq1, sirq2

Optional Properties:

- bias-bus-hold:  No arguments. The specified pins should retain the previous

                  state value.

- bias-high-impedance: No arguments. The specified pins should be configured

                  as high impedance.

- bias-pull-down: No arguments. The specified pins should be configured as

                  pull down.

- bias-pull-up:   No arguments. The specified pins should be configured as

                  pull up.

- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified

                  pins

- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified

                  pins

- slew-rate:      Integer. Sets slew rate for the specified pins.

                  Valid values are:

                  <0>  - Slow

                  <1>  - Fast

- drive-strength: Integer. Selects the drive strength for the specified

                  pins in mA.

                  Valid values are:

                  <2>

                  <4>

                  <8>

                  <12>

Example:

          pinctrl: pinctrl@e01b0000 {

                  compatible = "actions,s900-pinctrl";

                  reg = <0x0 0xe01b0000 0x0 0x1000>;

                  clocks = <&cmu CLK_GPIO>;

                  uart2-default: uart2-default {

                          pinmux {

                                  groups = "lvds_oep_odn_mfp";

                                  function = "uart2";

                          };

                          pinconf {

                                  groups = "lvds_oep_odn_drv";

                                  drive-strength = <12>;

                          };

                  };

          };

  "allwinner,sun50i-a64-pinctrl"

  "allwinner,sun50i-a64-r-pinctrl"

  "allwinner,sun50i-h5-pinctrl"

  "allwinner,sun50i-h6-pinctrl"

  "nextthing,gr8-pinctrl"

- reg: Should contain the register physical address and length for the

	Available functions and groups (function: group0, group1...):

		gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,

		      i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,

		      spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,

		      uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0

		      spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2,

		      uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2,

		      uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1,

		      uart5nocts

		cpuclkout: cpuclkoutgrp0

		udlclkout: udlclkoutgrp0

		i2c1: i2c1grp0

		spi0: spi0grp0

		spi1: spi1grp0

		pciedebug: pciedebuggrp0

		uart0: uart0grp0, uart0grp1

		uart1: uart1grp0

		uart2: uart2grp0, uart2grp1

		uart0: uart0grp0, uart0grp1, uart0grp2

		uart1: uart1grp0, uart1grp1

		uart2: uart2grp0, uart2grp1, uart2grp2

		uart3: uart3grp0

		uart4: uart4grp0

		uart5: uart5grp0

		uart4: uart4grp0, uart4grp1

		uart5: uart5grp0, uart5grp1, uart5nocts

		nand: nandgrp0

		sdio0: sdio0grp0

		sdio1: sdio1grp0

* Freescale i.MX6 SLL IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part

and usage.

Required properties:

- compatible: "fsl,imx6sll-iomuxc"

- fsl,pins: each entry consists of 6 integers and represents the mux and config

  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val

  input_val> are specified using a PIN_FUNC_ID macro, which can be found in

  imx6sll-pinfunc.h under device tree source folder.  The last integer CONFIG is

  the pad setting value like pull-up on this pin.  Please refer to i.MX6SLL

  Reference Manual for detailed CONFIG settings.

CONFIG bits definition:

PAD_CTL_LVE			(1 << 22)

PAD_CTL_HYS                     (1 << 16)

PAD_CTL_PUS_100K_DOWN           (0 << 14)

PAD_CTL_PUS_47K_UP              (1 << 14)

PAD_CTL_PUS_100K_UP             (2 << 14)

PAD_CTL_PUS_22K_UP              (3 << 14)

PAD_CTL_PUE                     (1 << 13)

PAD_CTL_PKE                     (1 << 12)

PAD_CTL_ODE                     (1 << 11)

PAD_CTL_SPEED_LOW               (0 << 6)

PAD_CTL_SPEED_MED               (1 << 6)

PAD_CTL_SPEED_HIGH              (3 << 6)

PAD_CTL_DSE_DISABLE             (0 << 3)

PAD_CTL_DSE_260ohm              (1 << 3)

PAD_CTL_DSE_130ohm              (2 << 3)

PAD_CTL_DSE_87ohm               (3 << 3)

PAD_CTL_DSE_65ohm               (4 << 3)

PAD_CTL_DSE_52ohm               (5 << 3)

PAD_CTL_DSE_43ohm               (6 << 3)

PAD_CTL_DSE_37ohm               (7 << 3)

PAD_CTL_SRE_FAST                (1 << 0)

PAD_CTL_SRE_SLOW                (0 << 0)

Refer to imx6sll-pinfunc.h in device tree source folder for all available

imx6sll PIN_FUNC_ID.

ImgTec TZ1090 PDC pin controller

Required properties:

- compatible: "img,tz1090-pdc-pinctrl"

- reg: Should contain the register physical address and length of the

  SOC_GPIO_CONTROL registers in the PDC register region.

Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".

TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number

of subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those pin(s)/group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.

The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function. For this reason, even seemingly boolean

values are actually tristates in this binding: unspecified, off, or on.

Unspecified is represented as an absent property, and off/on are represented as

integer values 0 and 1.

Required subnode-properties:

- tz1090,pins : An array of strings. Each string contains the name of a pin or

  group. Valid values for these names are listed below.

Optional subnode-properties:

- tz1090,function: A string containing the name of the function to mux to the

  pin or group. Valid values for function names are listed below, including

  which pingroups can be muxed to them.

- supported generic pinconfig properties (for further details see

  Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):

  - bias-disable

  - bias-high-impedance

  - bias-bus-hold

  - bias-pull-up

  - bias-pull-down

  - input-schmitt-enable

  - input-schmitt-disable

  - drive-strength: Integer, control drive strength of pins in mA.

      2: 2mA

      4: 4mA

      8: 8mA

      12: 12mA

  - low-power-enable: Flag, power-on-start weak pull-down for invalid power.

  - low-power-disable: Flag, power-on-start weak pull-down disabled.

Note that many of these properties are only valid for certain specific pins

or groups. See the TZ1090 TRM for complete details regarding which groups

support which functionality. The Linux pinctrl driver may also be a useful

reference.

Valid values for pin and group names are:

  pins:

    These all support bias-high-impediance, bias-pull-up, bias-pull-down, and

    bias-bus-hold (which can also be provided to any of the groups below to set

    it for all gpio pins in that group).

    gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power.

  mux groups:

    These all support function.

    gpio0

        pins:       gpio0.

        function:   ir_mod_stable_out.

    gpio1

        pins:       gpio1.

        function:   ir_mod_power_out.

  drive groups:

    These support input-schmitt-enable, input-schmitt-disable,

    drive-strength, low-power-enable, and low-power-disable.

    pdc

        pins:   gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data,

                ext_power.

Example:

	pinctrl_pdc: pinctrl@2006500 {

		#gpio-range-cells = <3>;

		compatible = "img,tz1090-pdc-pinctrl";

		reg = <0x02006500 0x100>;

	};

Example board file extracts:

	&pinctrl_pdc {

		pinctrl-names = "default";

		pinctrl-0 = <&syswake_default>;

		syswake_default: syswakes {

			syswake_cfg {

				tz1090,pins =	"sys_wake0",

						"sys_wake1",

						"sys_wake2";

				pull-up;

			};

		};

		irmod_default: irmod {

			gpio0_cfg {

				tz1090,pins =	"gpio0";

				tz1090,function = "ir_mod_stable_out";

			};

			gpio1_cfg {

				tz1090,pins =	"gpio1";

				tz1090,function = "ir_mod_power_out";

			};

		};

	};

	ir: ir@2006200 {

		pinctrl-names = "default";

		pinctrl-0 = <&irmod_default>;

	};