Loading drivers/gpu/msm/adreno_a6xx.c +14 −18 Original line number Diff line number Diff line Loading @@ -116,10 +116,6 @@ static u32 a615_pwrup_reglist[] = { A6XX_UCHE_GBIF_GX_CONFIG, }; static u32 a612_pwrup_reglist[] = { A6XX_RBBM_PERFCTR_CNTL, }; static int a6xx_get_cp_init_cmds(struct adreno_device *adreno_dev); static int a6xx_init(struct adreno_device *adreno_dev) Loading Loading @@ -315,9 +311,7 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) reglist[items++] = REGLIST(a6xx_pwrup_reglist); /* Add target specific registers */ if (adreno_is_a612(adreno_dev)) reglist[items++] = REGLIST(a612_pwrup_reglist); else if (adreno_is_a615_family(adreno_dev)) if (adreno_is_a615_family(adreno_dev)) reglist[items++] = REGLIST(a615_pwrup_reglist); else if (adreno_is_a650_family(adreno_dev)) reglist[items++] = REGLIST(a650_pwrup_reglist); Loading Loading @@ -349,6 +343,10 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) lock->list_length += 2; *dest++ = A6XX_RBBM_PERFCTR_CNTL; *dest++ = 1; lock->list_length += 2; /* * The overall register list is composed of * 1. Static IFPC-only registers Loading Loading @@ -2574,24 +2572,22 @@ static int a6xx_perfcounter_update(struct adreno_device *adreno_dev, goto update; } if (data[offset] == A6XX_RBBM_PERFCTR_CNTL) break; offset += 2; } /* * For a612 targets A6XX_RBBM_PERFCTR_CNTL needs to be the last entry, * For all targets A6XX_RBBM_PERFCTR_CNTL needs to be the last entry, * so overwrite the existing A6XX_RBBM_PERFCNTL_CTRL and add it back to * the end. All other targets just append the new counter to the end. * the end. */ if (adreno_is_a612(adreno_dev)) { data[offset - 2] = reg->select; data[offset - 1] = reg->countable; data[offset] = A6XX_RBBM_PERFCTR_CNTL, data[offset + 1] = 1; } else { data[offset] = reg->select; data[offset + 1] = reg->countable; } data[offset + 2] = A6XX_RBBM_PERFCTR_CNTL, data[offset + 3] = 1; lock->list_length += 2; Loading Loading
drivers/gpu/msm/adreno_a6xx.c +14 −18 Original line number Diff line number Diff line Loading @@ -116,10 +116,6 @@ static u32 a615_pwrup_reglist[] = { A6XX_UCHE_GBIF_GX_CONFIG, }; static u32 a612_pwrup_reglist[] = { A6XX_RBBM_PERFCTR_CNTL, }; static int a6xx_get_cp_init_cmds(struct adreno_device *adreno_dev); static int a6xx_init(struct adreno_device *adreno_dev) Loading Loading @@ -315,9 +311,7 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) reglist[items++] = REGLIST(a6xx_pwrup_reglist); /* Add target specific registers */ if (adreno_is_a612(adreno_dev)) reglist[items++] = REGLIST(a612_pwrup_reglist); else if (adreno_is_a615_family(adreno_dev)) if (adreno_is_a615_family(adreno_dev)) reglist[items++] = REGLIST(a615_pwrup_reglist); else if (adreno_is_a650_family(adreno_dev)) reglist[items++] = REGLIST(a650_pwrup_reglist); Loading Loading @@ -349,6 +343,10 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) lock->list_length += 2; *dest++ = A6XX_RBBM_PERFCTR_CNTL; *dest++ = 1; lock->list_length += 2; /* * The overall register list is composed of * 1. Static IFPC-only registers Loading Loading @@ -2574,24 +2572,22 @@ static int a6xx_perfcounter_update(struct adreno_device *adreno_dev, goto update; } if (data[offset] == A6XX_RBBM_PERFCTR_CNTL) break; offset += 2; } /* * For a612 targets A6XX_RBBM_PERFCTR_CNTL needs to be the last entry, * For all targets A6XX_RBBM_PERFCTR_CNTL needs to be the last entry, * so overwrite the existing A6XX_RBBM_PERFCNTL_CTRL and add it back to * the end. All other targets just append the new counter to the end. * the end. */ if (adreno_is_a612(adreno_dev)) { data[offset - 2] = reg->select; data[offset - 1] = reg->countable; data[offset] = A6XX_RBBM_PERFCTR_CNTL, data[offset + 1] = 1; } else { data[offset] = reg->select; data[offset + 1] = reg->countable; } data[offset + 2] = A6XX_RBBM_PERFCTR_CNTL, data[offset + 3] = 1; lock->list_length += 2; Loading