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Commit 76d7961f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_fixes_5.3_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS fixes from Paul Burton:
 "A few MIPS fixes for 5.3:

   - Various switch fall through annotations to fixup warnings & errors
     resulting from -Wimplicit-fallthrough.

   - A fix for systems (at least jazz) using an i8253 PIT as clocksource
     when it's not suitably configured.

   - Set struct cacheinfo's cpu_map_populated field to true, indicating
     that we filled in cache info detected from cop0 registers &
     avoiding complaints about that info being (intentionally) missing
     in devicetree"

* tag 'mips_fixes_5.3_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: BCM63XX: Mark expected switch fall-through
  MIPS: OProfile: Mark expected switch fall-throughs
  MIPS: Annotate fall-through in Cavium Octeon code
  MIPS: Annotate fall-through in kvm/emulate.c
  mips: fix cacheinfo
  MIPS: kernel: only use i8253 clocksource with periodic clockevent
parents f4eb1423 74034a09

arch/mips/cavium-octeon/octeon-usb.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -398,6 +398,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) 
	default:

	default:

		dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",

		dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",

			clock_rate);

			clock_rate);

		/* fall through */

	case 100000000:

	case 100000000:

		mpll_mul = 0x19;

		mpll_mul = 0x19;

		if (ref_clk_sel < 2)

		if (ref_clk_sel < 2)

arch/mips/kernel/cacheinfo.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -69,6 +69,8 @@ static int __populate_cache_leaves(unsigned int cpu) 
	if (c->tcache.waysize)

	if (c->tcache.waysize)

		populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);

		populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);





	this_cpu_ci->cpu_map_populated = true;



	return 0;

	return 0;

}

}

arch/mips/kernel/i8253.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -32,7 +32,8 @@ void __init setup_pit_timer(void) 




static int __init init_pit_clocksource(void)

static int __init init_pit_clocksource(void)

{

{

	if (num_possible_cpus() > 1) /* PIT does not scale! */

	if (num_possible_cpus() > 1 || /* PIT does not scale! */

	    !clockevent_state_periodic(&i8253_clockevent))

		return 0;

		return 0;





	return clocksource_i8253_init();

	return clocksource_i8253_init();

arch/mips/kvm/emulate.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -140,6 +140,7 @@ static int kvm_compute_return_epc(struct kvm_vcpu *vcpu, unsigned long instpc, 
		/* These are unconditional and in j_format. */

		/* These are unconditional and in j_format. */

	case jal_op:

	case jal_op:

		arch->gprs[31] = instpc + 8;

		arch->gprs[31] = instpc + 8;

		/* fall through */

	case j_op:

	case j_op:

		epc += 4;

		epc += 4;

		epc >>= 28;

		epc >>= 28;

arch/mips/oprofile/op_model_mipsxx.c

+13 −0
Original line number Original line Diff line number Diff line
@@ -172,12 +172,15 @@ static void mipsxx_cpu_setup(void *args) 
	case 4:

	case 4:

		w_c0_perfctrl3(0);

		w_c0_perfctrl3(0);

		w_c0_perfcntr3(reg.counter[3]);

		w_c0_perfcntr3(reg.counter[3]);

		/* fall through */

	case 3:

	case 3:

		w_c0_perfctrl2(0);

		w_c0_perfctrl2(0);

		w_c0_perfcntr2(reg.counter[2]);

		w_c0_perfcntr2(reg.counter[2]);

		/* fall through */

	case 2:

	case 2:

		w_c0_perfctrl1(0);

		w_c0_perfctrl1(0);

		w_c0_perfcntr1(reg.counter[1]);

		w_c0_perfcntr1(reg.counter[1]);

		/* fall through */

	case 1:

	case 1:

		w_c0_perfctrl0(0);

		w_c0_perfctrl0(0);

		w_c0_perfcntr0(reg.counter[0]);

		w_c0_perfcntr0(reg.counter[0]);
@@ -195,10 +198,13 @@ static void mipsxx_cpu_start(void *args) 
	switch (counters) {

	switch (counters) {

	case 4:

	case 4:

		w_c0_perfctrl3(WHAT | reg.control[3]);

		w_c0_perfctrl3(WHAT | reg.control[3]);

		/* fall through */

	case 3:

	case 3:

		w_c0_perfctrl2(WHAT | reg.control[2]);

		w_c0_perfctrl2(WHAT | reg.control[2]);

		/* fall through */

	case 2:

	case 2:

		w_c0_perfctrl1(WHAT | reg.control[1]);

		w_c0_perfctrl1(WHAT | reg.control[1]);

		/* fall through */

	case 1:

	case 1:

		w_c0_perfctrl0(WHAT | reg.control[0]);

		w_c0_perfctrl0(WHAT | reg.control[0]);

	}

	}
@@ -215,10 +221,13 @@ static void mipsxx_cpu_stop(void *args) 
	switch (counters) {

	switch (counters) {

	case 4:

	case 4:

		w_c0_perfctrl3(0);

		w_c0_perfctrl3(0);

		/* fall through */

	case 3:

	case 3:

		w_c0_perfctrl2(0);

		w_c0_perfctrl2(0);

		/* fall through */

	case 2:

	case 2:

		w_c0_perfctrl1(0);

		w_c0_perfctrl1(0);

		/* fall through */

	case 1:

	case 1:

		w_c0_perfctrl0(0);

		w_c0_perfctrl0(0);

	}

	}
@@ -236,6 +245,7 @@ static int mipsxx_perfcount_handler(void) 




	switch (counters) {

	switch (counters) {

#define HANDLE_COUNTER(n)						\

#define HANDLE_COUNTER(n)						\

	/* fall through */						\

	case n + 1:							\

	case n + 1:							\

		control = r_c0_perfctrl ## n();				\

		control = r_c0_perfctrl ## n();				\

		counter = r_c0_perfcntr ## n();				\

		counter = r_c0_perfcntr ## n();				\
@@ -297,12 +307,15 @@ static void reset_counters(void *arg) 
	case 4:

	case 4:

		w_c0_perfctrl3(0);

		w_c0_perfctrl3(0);

		w_c0_perfcntr3(0);

		w_c0_perfcntr3(0);

		/* fall through */

	case 3:

	case 3:

		w_c0_perfctrl2(0);

		w_c0_perfctrl2(0);

		w_c0_perfcntr2(0);

		w_c0_perfcntr2(0);

		/* fall through */

	case 2:

	case 2:

		w_c0_perfctrl1(0);

		w_c0_perfctrl1(0);

		w_c0_perfcntr1(0);

		w_c0_perfcntr1(0);

		/* fall through */

	case 1:

	case 1:

		w_c0_perfctrl0(0);

		w_c0_perfctrl0(0);

		w_c0_perfcntr0(0);

		w_c0_perfcntr0(0);