Commit 7642984b authored Jun 07, 2017 by Catherine Sullivan Committed by Jeff Kirsher Jun 20, 2017

i40e: Handle PE_CRITERR properly with IWARP enabled



When IWARP is enabled, we weren't clearing the PE_CRITERR, just logging
it and removing it from the mask. We need to do a corer to reset the
PE_CRITERR register, so set the bit for that as we handle the
interrupt.

We should also be checking for the error against the PFINT_ICR0 register,
and only need to clear it in the value getting written to
PFINT_ICR0_ENA.

Signed-off-by: Catherine Sullivan <catherine.sullivan@intel.com>
Signed-off-by: Mitch Williams <mitch.a.williams@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

parent 2e5c26ea

drivers/net/ethernet/intel/i40e/i40e_main.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -3684,10 +3684,10 @@ static irqreturn_t i40e_intr(int irq, void *data)
		pf->sw_int_count++;

		if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
		(ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
		(icr0 & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
		ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
		icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
		dev_dbg(&pf->pdev->dev, "cleared PE_CRITERR\n");
		set_bit(__I40E_CORE_RESET_REQUESTED, pf->state);
		}

		/* only q0 is used in MSI/Legacy mode, and none are used in MSIX */