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Commit 7624fc01 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/mpeg: convert to new-style nvkm_engine 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 6f41c7c5

drivers/gpu/drm/nouveau/include/nvkm/core/engine.h

+0 −2
Original line number Diff line number Diff line
@@ -19,8 +19,6 @@ struct nvkm_engine { 


	struct list_head contexts;

	spinlock_t lock;



	void (*tile_prog)(struct nvkm_engine *, int region);

};



struct nvkm_engine_func {

drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h

+5 −34
Original line number Diff line number Diff line 
#ifndef __NVKM_MPEG_H__

#define __NVKM_MPEG_H__

#include <core/engine.h>



struct nvkm_mpeg {

	struct nvkm_engine engine;

};



#define nvkm_mpeg_create(p,e,c,d)                                           \

	nvkm_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d))

#define nvkm_mpeg_destroy(d)                                                \

	nvkm_engine_destroy(&(d)->engine)

#define nvkm_mpeg_init(d)                                                   \

	nvkm_engine_init_old(&(d)->engine)

#define nvkm_mpeg_fini(d,s)                                                 \

	nvkm_engine_fini_old(&(d)->engine, (s))



#define _nvkm_mpeg_dtor _nvkm_engine_dtor

#define _nvkm_mpeg_init _nvkm_engine_init

#define _nvkm_mpeg_fini _nvkm_engine_fini



extern struct nvkm_oclass nv31_mpeg_oclass;

extern struct nvkm_oclass nv40_mpeg_oclass;

extern struct nvkm_oclass nv44_mpeg_oclass;

extern struct nvkm_oclass nv50_mpeg_oclass;

extern struct nvkm_oclass g84_mpeg_oclass;

extern struct nvkm_oclass nv40_mpeg_sclass[];

void nv31_mpeg_intr(struct nvkm_subdev *);

void nv31_mpeg_tile_prog(struct nvkm_engine *, int);

int  nv31_mpeg_init(struct nvkm_object *);



extern struct nvkm_ofuncs nv50_mpeg_ofuncs;

int  nv50_mpeg_context_ctor(struct nvkm_object *, struct nvkm_object *,

			    struct nvkm_oclass *, void *, u32,

			    struct nvkm_object **);

void nv50_mpeg_intr(struct nvkm_subdev *);

int  nv50_mpeg_init(struct nvkm_object *);

int nv31_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);

int nv40_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);

int nv44_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);

int nv50_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);

int g84_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);

#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+27 −27
Original line number Diff line number Diff line
@@ -381,7 +381,7 @@ nv31_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv17_fifo_new,

	.gr = nv30_gr_new,

//	.mpeg = nv31_mpeg_new,

	.mpeg = nv31_mpeg_new,

	.sw = nv10_sw_new,

};
@@ -403,7 +403,7 @@ nv34_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv17_fifo_new,

	.gr = nv34_gr_new,

//	.mpeg = nv31_mpeg_new,

	.mpeg = nv31_mpeg_new,

	.sw = nv10_sw_new,

};
@@ -446,7 +446,7 @@ nv36_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv17_fifo_new,

	.gr = nv35_gr_new,

//	.mpeg = nv31_mpeg_new,

	.mpeg = nv31_mpeg_new,

	.sw = nv10_sw_new,

};
@@ -470,7 +470,7 @@ nv40_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,

	.mpeg = nv40_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -495,7 +495,7 @@ nv41_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,

	.mpeg = nv40_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -520,7 +520,7 @@ nv42_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,

	.mpeg = nv40_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -545,7 +545,7 @@ nv43_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,

	.mpeg = nv40_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -570,7 +570,7 @@ nv44_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv44_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -595,7 +595,7 @@ nv45_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -620,7 +620,7 @@ nv46_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv44_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -645,7 +645,7 @@ nv47_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -670,7 +670,7 @@ nv49_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -695,7 +695,7 @@ nv4a_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv44_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -720,7 +720,7 @@ nv4b_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -745,7 +745,7 @@ nv4c_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv44_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -770,7 +770,7 @@ nv4e_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv44_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -798,7 +798,7 @@ nv50_chipset = { 
	.dma = nv50_dma_new,

	.fifo = nv50_fifo_new,

	.gr = nv50_gr_new,

//	.mpeg = nv50_mpeg_new,

	.mpeg = nv50_mpeg_new,

	.pm = nv50_pm_new,

	.sw = nv50_sw_new,

};
@@ -823,7 +823,7 @@ nv63_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv44_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -848,7 +848,7 @@ nv67_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv44_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -873,7 +873,7 @@ nv68_chipset = { 
	.dma = nv04_dma_new,

	.fifo = nv40_fifo_new,

	.gr = nv44_gr_new,

//	.mpeg = nv44_mpeg_new,

	.mpeg = nv44_mpeg_new,

	.pm = nv40_pm_new,

	.sw = nv10_sw_new,

};
@@ -903,7 +903,7 @@ nv84_chipset = { 
	.dma = nv50_dma_new,

	.fifo = g84_fifo_new,

	.gr = g84_gr_new,

//	.mpeg = g84_mpeg_new,

	.mpeg = g84_mpeg_new,

	.pm = g84_pm_new,

	.sw = nv50_sw_new,

	.vp = g84_vp_new,
@@ -934,7 +934,7 @@ nv86_chipset = { 
	.dma = nv50_dma_new,

	.fifo = g84_fifo_new,

	.gr = g84_gr_new,

//	.mpeg = g84_mpeg_new,

	.mpeg = g84_mpeg_new,

	.pm = g84_pm_new,

	.sw = nv50_sw_new,

	.vp = g84_vp_new,
@@ -965,7 +965,7 @@ nv92_chipset = { 
	.dma = nv50_dma_new,

	.fifo = g84_fifo_new,

	.gr = g84_gr_new,

//	.mpeg = g84_mpeg_new,

	.mpeg = g84_mpeg_new,

	.pm = g84_pm_new,

	.sw = nv50_sw_new,

	.vp = g84_vp_new,
@@ -996,7 +996,7 @@ nv94_chipset = { 
	.dma = nv50_dma_new,

	.fifo = g84_fifo_new,

	.gr = g84_gr_new,

//	.mpeg = g84_mpeg_new,

	.mpeg = g84_mpeg_new,

	.pm = g84_pm_new,

	.sw = nv50_sw_new,

	.vp = g84_vp_new,
@@ -1025,7 +1025,7 @@ nv96_chipset = { 
	.fifo = g84_fifo_new,

	.gr = g84_gr_new,

	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,

	.mpeg = g84_mpeg_new,

	.vp = g84_vp_new,

	.cipher = g84_cipher_new,

	.bsp = g84_bsp_new,
@@ -1089,7 +1089,7 @@ nva0_chipset = { 
	.dma = nv50_dma_new,

	.fifo = g84_fifo_new,

	.gr = gt200_gr_new,

//	.mpeg = g84_mpeg_new,

	.mpeg = g84_mpeg_new,

	.pm = gt200_pm_new,

	.sw = nv50_sw_new,

	.vp = g84_vp_new,
@@ -1120,7 +1120,7 @@ nva3_chipset = { 
	.dma = nv50_dma_new,

	.fifo = g84_fifo_new,

	.gr = gt215_gr_new,

//	.mpeg = g84_mpeg_new,

	.mpeg = g84_mpeg_new,

	.mspdec = gt215_mspdec_new,

	.msppp = gt215_msppp_new,

	.msvld = gt215_msvld_new,

drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c

+0 −3
Original line number Diff line number Diff line
@@ -32,13 +32,10 @@ nv30_identify(struct nvkm_device *device) 
	case 0x35:

		break;

	case 0x31:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;

		break;

	case 0x36:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;

		break;

	case 0x34:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;

		break;

	default:

		return -EINVAL;

drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c

+0 −16
Original line number Diff line number Diff line
@@ -28,52 +28,36 @@ nv40_identify(struct nvkm_device *device) 
{

	switch (device->chipset) {

	case 0x40:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;

		break;

	case 0x41:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;

		break;

	case 0x42:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;

		break;

	case 0x43:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;

		break;

	case 0x45:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x47:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x49:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x4b:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x44:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x46:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x4a:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x4c:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x4e:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x63:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x67:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	case 0x68:

		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;

		break;

	default:

		return -EINVAL;