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Commit 75d2b253 authored by Anirudh Venkataramanan's avatar Anirudh Venkataramanan Committed by Jeff Kirsher
Browse files

ice: Add support to detect SR-IOV capability and mailbox queues 



Mailbox queue is a type of control queue that's used for communication
between PF and VF. This patch adds code to initialize, configure and
use mailbox queues.

This patch also adds support to detect and parse SR-IOV capabilities
returned by the hardware.

Signed-off-by: default avatarAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 16fc087b

drivers/net/ethernet/intel/ice/ice.h

+5 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ extern const char ice_drv_ver[]; 
#define ICE_INT_NAME_STR_LEN	(IFNAMSIZ + 16)

#define ICE_ETHTOOL_FWVER_LEN	32

#define ICE_AQ_LEN		64

#define ICE_MBXQ_LEN		64

#define ICE_MIN_MSIX		2

#define ICE_NO_VSI		0xffff

#define ICE_MAX_VSI_ALLOC	130
@@ -63,6 +64,7 @@ extern const char ice_drv_ver[]; 
#define ICE_RES_MISC_VEC_ID	(ICE_RES_VALID_BIT - 1)

#define ICE_INVAL_Q_INDEX	0xffff

#define ICE_INVAL_VFID		256

#define ICE_MAX_VF_COUNT	256



#define ICE_VSIQF_HKEY_ARRAY_SIZE	((VSIQF_HKEY_MAX_INDEX + 1) *	4)
@@ -134,6 +136,7 @@ enum ice_state { 
	__ICE_SUSPENDED,		/* set on module remove path */

	__ICE_RESET_FAILED,		/* set by reset/rebuild */

	__ICE_ADMINQ_EVENT_PENDING,

	__ICE_MAILBOXQ_EVENT_PENDING,

	__ICE_MDD_EVENT_PENDING,

	__ICE_FLTR_OVERFLOW_PROMISC,

	__ICE_CFG_BUSY,
@@ -240,6 +243,7 @@ enum ice_pf_flags { 
	ICE_FLAG_MSIX_ENA,

	ICE_FLAG_FLTR_SYNC,

	ICE_FLAG_RSS_ENA,

	ICE_FLAG_SRIOV_CAPABLE,

	ICE_PF_FLAGS_NBITS		/* must be last */

};
@@ -255,6 +259,7 @@ struct ice_pf { 


	struct ice_vsi **vsi;		/* VSIs created by the driver */

	struct ice_sw *first_sw;	/* first switch created by firmware */

	u16 num_vfs_supported;		/* num VFs supported for this PF */

	DECLARE_BITMAP(state, __ICE_STATE_NBITS);

	DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS);

	DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS);

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

+2 −0
Original line number Diff line number Diff line
@@ -87,6 +87,8 @@ struct ice_aqc_list_caps { 
/* Device/Function buffer entry, repeated per reported capability */

struct ice_aqc_list_caps_elem {

	__le16 cap;

#define ICE_AQC_CAPS_SRIOV				0x0012

#define ICE_AQC_CAPS_VF					0x0013

#define ICE_AQC_CAPS_VSI				0x0017

#define ICE_AQC_CAPS_RSS				0x0040

#define ICE_AQC_CAPS_RXQS				0x0041

drivers/net/ethernet/intel/ice/ice_common.c

+22 −0
Original line number Diff line number Diff line
@@ -1406,6 +1406,28 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, 
		u16 cap = le16_to_cpu(cap_resp->cap);



		switch (cap) {

		case ICE_AQC_CAPS_SRIOV:

			caps->sr_iov_1_1 = (number == 1);

			ice_debug(hw, ICE_DBG_INIT,

				  "HW caps: SR-IOV = %d\n", caps->sr_iov_1_1);

			break;

		case ICE_AQC_CAPS_VF:

			if (dev_p) {

				dev_p->num_vfs_exposed = number;

				ice_debug(hw, ICE_DBG_INIT,

					  "HW caps: VFs exposed = %d\n",

					  dev_p->num_vfs_exposed);

			} else if (func_p) {

				func_p->num_allocd_vfs = number;

				func_p->vf_base_id = logical_id;

				ice_debug(hw, ICE_DBG_INIT,

					  "HW caps: VFs allocated = %d\n",

					  func_p->num_allocd_vfs);

				ice_debug(hw, ICE_DBG_INIT,

					  "HW caps: VF base_id = %d\n",

					  func_p->vf_base_id);

			}

			break;

		case ICE_AQC_CAPS_VSI:

			if (dev_p) {

				dev_p->num_vsi_allocd_to_host = number;

drivers/net/ethernet/intel/ice/ice_controlq.c

+45 −1
Original line number Diff line number Diff line
@@ -32,6 +32,36 @@ static void ice_adminq_init_regs(struct ice_hw *hw) 
	cq->rq.head_mask = PF_FW_ARQH_ARQH_M;

}



/**

 * ice_mailbox_init_regs - Initialize Mailbox registers

 * @hw: pointer to the hardware structure

 *

 * This assumes the alloc_sq and alloc_rq functions have already been called

 */

static void ice_mailbox_init_regs(struct ice_hw *hw)

{

	struct ice_ctl_q_info *cq = &hw->mailboxq;



	/* set head and tail registers in our local struct */

	cq->sq.head = PF_MBX_ATQH;

	cq->sq.tail = PF_MBX_ATQT;

	cq->sq.len = PF_MBX_ATQLEN;

	cq->sq.bah = PF_MBX_ATQBAH;

	cq->sq.bal = PF_MBX_ATQBAL;

	cq->sq.len_mask = PF_MBX_ATQLEN_ATQLEN_M;

	cq->sq.len_ena_mask = PF_MBX_ATQLEN_ATQENABLE_M;

	cq->sq.head_mask = PF_MBX_ATQH_ATQH_M;



	cq->rq.head = PF_MBX_ARQH;

	cq->rq.tail = PF_MBX_ARQT;

	cq->rq.len = PF_MBX_ARQLEN;

	cq->rq.bah = PF_MBX_ARQBAH;

	cq->rq.bal = PF_MBX_ARQBAL;

	cq->rq.len_mask = PF_MBX_ARQLEN_ARQLEN_M;

	cq->rq.len_ena_mask = PF_MBX_ARQLEN_ARQENABLE_M;

	cq->rq.head_mask = PF_MBX_ARQH_ARQH_M;

}



/**

 * ice_check_sq_alive

 * @hw: pointer to the hw struct
@@ -639,6 +669,10 @@ static enum ice_status ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type) 
		ice_adminq_init_regs(hw);

		cq = &hw->adminq;

		break;

	case ICE_CTL_Q_MAILBOX:

		ice_mailbox_init_regs(hw);

		cq = &hw->mailboxq;

		break;

	default:

		return ICE_ERR_PARAM;

	}
@@ -696,7 +730,12 @@ enum ice_status ice_init_all_ctrlq(struct ice_hw *hw) 
	if (ret_code)

		return ret_code;



	return ice_init_check_adminq(hw);

	ret_code = ice_init_check_adminq(hw);

	if (ret_code)

		return ret_code;



	/* Init Mailbox queue */

	return ice_init_ctrlq(hw, ICE_CTL_Q_MAILBOX);

}



/**
@@ -714,6 +753,9 @@ static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type) 
		if (ice_check_sq_alive(hw, cq))

			ice_aq_q_shutdown(hw, true);

		break;

	case ICE_CTL_Q_MAILBOX:

		cq = &hw->mailboxq;

		break;

	default:

		return;

	}
@@ -736,6 +778,8 @@ void ice_shutdown_all_ctrlq(struct ice_hw *hw) 
{

	/* Shutdown FW admin queue */

	ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);

	/* Shutdown PF-VF Mailbox */

	ice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX);

}



/**

drivers/net/ethernet/intel/ice/ice_controlq.h

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 


/* Maximum buffer lengths for all control queue types */

#define ICE_AQ_MAX_BUF_LEN 4096

#define ICE_MBXQ_MAX_BUF_LEN 4096



#define ICE_CTL_Q_DESC(R, i) \

	(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
@@ -28,6 +29,7 @@ 
enum ice_ctl_q {

	ICE_CTL_Q_UNKNOWN = 0,

	ICE_CTL_Q_ADMIN,

	ICE_CTL_Q_MAILBOX,

};



/* Control Queue default settings */