Loading qcom/lahaina-coresight.dtsi +2 −1 Original line number Diff line number Diff line Loading @@ -107,6 +107,7 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; coresight-ctis = <&cti0_swao &cti3_swao>; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading Loading @@ -153,7 +154,7 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti0>; coresight-ctis = <&cti0 &cti3_swao>; coresight-csr = <&csr>; clocks = <&clock_aop QDSS_CLK>; Loading Loading
qcom/lahaina-coresight.dtsi +2 −1 Original line number Diff line number Diff line Loading @@ -107,6 +107,7 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; coresight-ctis = <&cti0_swao &cti3_swao>; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading Loading @@ -153,7 +154,7 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti0>; coresight-ctis = <&cti0 &cti3_swao>; coresight-csr = <&csr>; clocks = <&clock_aop QDSS_CLK>; Loading