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Commit 7523b0c3 authored by Hui Li's avatar Hui Li
Browse files

msm: kgsl: configure macrotiling channels for A680 



For macrotiling change on a680, will affect RB, SP and TP
0 means UBWC 3.0, 1 means UBWC 3.1, this change configures
the RBBM hardware accordingly.

Change-Id: Ife8325a88e37b5b81ef6060c11edb7b7b2aab165
Signed-off-by: default avatarHui Li <hul@codeaurora.org>
parent 9efe49ec

drivers/gpu/msm/adreno_a6xx.c

+7 −0
Original line number Diff line number Diff line
@@ -652,6 +652,13 @@ void a6xx_start(struct adreno_device *adreno_dev) 
		break;

	}



	/*

	 * For macrotiling change on a680,  will affect RB, SP and TP

	 * 0 means UBWC 3.0, 1 means UBWC 3.1

	 */

	if (adreno_is_a680(adreno_dev))

		kgsl_regwrite(device, A6XX_RBBM_NC_MODE_CNTL, 1);



	if (!WARN_ON(!adreno_dev->highest_bank_bit)) {

		hbb_lo = (adreno_dev->highest_bank_bit - 13) & 3;

		hbb_hi = ((adreno_dev->highest_bank_bit - 13) >> 2) & 1;