Merge "clk: qcom: gcc: Add support for edp ref clock for Yupik" (74e7790a) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/qcom/gcc-yupik.c

+14 −0

Original line number	Original line	Diff line number	Diff line
	@@ -2173,6 +2173,19 @@ static struct clk_branch gcc_pcie_clkref_en = {
	},		},
	};		};

			static struct clk_branch gcc_edp_clkref_en = {
			.halt_reg = 0x8c008,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x8c008,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "gcc_edp_clkref_en",
			.ops = &clk_branch2_ops,
			},
			},
			};

	static struct clk_branch gcc_pcie_throttle_core_clk = {		static struct clk_branch gcc_pcie_throttle_core_clk = {
	.halt_reg = 0x90018,		.halt_reg = 0x90018,
	.halt_check = BRANCH_HALT_SKIP,		.halt_check = BRANCH_HALT_SKIP,
	@@ -3510,6 +3523,7 @@ static struct clk_regmap *gcc_yupik_clocks[] = {
	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,		[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
	[GCC_VIDEO_MVP_THROTTLE_CORE_CLK] =		[GCC_VIDEO_MVP_THROTTLE_CORE_CLK] =
	&gcc_video_mvp_throttle_core_clk.clkr,		&gcc_video_mvp_throttle_core_clk.clkr,
			[GCC_EDP_CLKREF_EN] = &gcc_edp_clkref_en.clkr,
	};		};

	static const struct qcom_reset_map gcc_yupik_resets[] = {		static const struct qcom_reset_map gcc_yupik_resets[] = {

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -177,6 +177,7 @@
	#define GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK 167		#define GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK 167
	#define GCC_AGGRE_NOC_PCIE_TBU_CLK 168		#define GCC_AGGRE_NOC_PCIE_TBU_CLK 168
	#define GCC_PCIE_CLKREF_EN 169		#define GCC_PCIE_CLKREF_EN 169
			#define GCC_EDP_CLKREF_EN 170

	/* GCC power domains */		/* GCC power domains */
	#define GCC_PCIE_0_GDSC 0		#define GCC_PCIE_0_GDSC 0