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Commit 7447d562 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf updates from Ingo Molnar:
 "Most of the changes are for tooling, the main changes in this cycle were:

   - Improve Intel-PT hardware tracing support, both on the kernel and
     on the tooling side: PTWRITE instruction support, power events for
     C-state tracing, etc. (Adrian Hunter)

   - Add support to measure SMI cost to the x86 architecture, with
     tooling support in 'perf stat' (Kan Liang)

   - Support function filtering in 'perf ftrace', plus related
     improvements (Namhyung Kim)

   - Allow adding and removing fields to the default 'perf script'
     columns, using + or - as field prefixes to do so (Andi Kleen)

   - Allow resolving the DSO name with 'perf script -F brstack{sym,off},dso'
     (Mark Santaniello)

   - Add perf tooling unwind support for PowerPC (Paolo Bonzini)

   - ... and various other improvements as well"

* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (84 commits)
  perf auxtrace: Add CPU filter support
  perf intel-pt: Do not use TSC packets for calculating CPU cycles to TSC
  perf intel-pt: Update documentation to include new ptwrite and power events
  perf intel-pt: Add example script for power events and PTWRITE
  perf intel-pt: Synthesize new power and "ptwrite" events
  perf intel-pt: Move code in intel_pt_synth_events() to simplify attr setting
  perf intel-pt: Factor out intel_pt_set_event_name()
  perf intel-pt: Tidy messages into called function intel_pt_synth_event()
  perf intel-pt: Tidy Intel PT evsel lookup into separate function
  perf intel-pt: Join needlessly wrapped lines
  perf intel-pt: Remove unused instructions_sample_period
  perf intel-pt: Factor out common code synthesizing event samples
  perf script: Add synthesized Intel PT power and ptwrite events
  perf/x86/intel: Constify the 'lbr_desc[]' array and make a function static
  perf script: Add 'synth' field for synthesized event payloads
  perf auxtrace: Add itrace option to output power events
  perf auxtrace: Add itrace option to output ptwrite events
  tools include: Add byte-swapping macros to kernel.h
  perf script: Add 'synth' event type for synthesized events
  x86/insn: perf tools: Add new ptwrite instruction
  ...
parents 892ad5ac 23acd3e1

arch/x86/events/core.c

+10 −0
Original line number Diff line number Diff line
@@ -1750,6 +1750,8 @@ ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) 
	return ret;

}



static struct attribute_group x86_pmu_attr_group;



static int __init init_hw_perf_events(void)

{

	struct x86_pmu_quirk *quirk;
@@ -1813,6 +1815,14 @@ static int __init init_hw_perf_events(void) 
			x86_pmu_events_group.attrs = tmp;

	}



	if (x86_pmu.attrs) {

		struct attribute **tmp;



		tmp = merge_attr(x86_pmu_attr_group.attrs, x86_pmu.attrs);

		if (!WARN_ON(!tmp))

			x86_pmu_attr_group.attrs = tmp;

	}



	pr_info("... version:                %d\n",     x86_pmu.version);

	pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);

	pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);

arch/x86/events/intel/core.c

+63 −0
Original line number Diff line number Diff line
@@ -3160,6 +3160,19 @@ static int intel_pmu_cpu_prepare(int cpu) 
	return -ENOMEM;

}



static void flip_smm_bit(void *data)

{

	unsigned long set = *(unsigned long *)data;



	if (set > 0) {

		msr_set_bit(MSR_IA32_DEBUGCTLMSR,

			    DEBUGCTLMSR_FREEZE_IN_SMM_BIT);

	} else {

		msr_clear_bit(MSR_IA32_DEBUGCTLMSR,

			      DEBUGCTLMSR_FREEZE_IN_SMM_BIT);

	}

}



static void intel_pmu_cpu_starting(int cpu)

{

	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
@@ -3174,6 +3187,8 @@ static void intel_pmu_cpu_starting(int cpu) 


	cpuc->lbr_sel = NULL;



	flip_smm_bit(&x86_pmu.attr_freeze_on_smi);



	if (!cpuc->shared_regs)

		return;
@@ -3595,6 +3610,52 @@ static struct attribute *hsw_events_attrs[] = { 
	NULL

};



static ssize_t freeze_on_smi_show(struct device *cdev,

				  struct device_attribute *attr,

				  char *buf)

{

	return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);

}



static DEFINE_MUTEX(freeze_on_smi_mutex);



static ssize_t freeze_on_smi_store(struct device *cdev,

				   struct device_attribute *attr,

				   const char *buf, size_t count)

{

	unsigned long val;

	ssize_t ret;



	ret = kstrtoul(buf, 0, &val);

	if (ret)

		return ret;



	if (val > 1)

		return -EINVAL;



	mutex_lock(&freeze_on_smi_mutex);



	if (x86_pmu.attr_freeze_on_smi == val)

		goto done;



	x86_pmu.attr_freeze_on_smi = val;



	get_online_cpus();

	on_each_cpu(flip_smm_bit, &val, 1);

	put_online_cpus();

done:

	mutex_unlock(&freeze_on_smi_mutex);



	return count;

}



static DEVICE_ATTR_RW(freeze_on_smi);



static struct attribute *intel_pmu_attrs[] = {

	&dev_attr_freeze_on_smi.attr,

	NULL,

};



__init int intel_pmu_init(void)

{

	union cpuid10_edx edx;
@@ -3641,6 +3702,8 @@ __init int intel_pmu_init(void) 


	x86_pmu.max_pebs_events		= min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);





	x86_pmu.attrs			= intel_pmu_attrs;

	/*

	 * Quirk: v2 perfmon does not report fixed-purpose events, so

	 * assume at least 3 events, when not running in a hypervisor:

arch/x86/events/intel/lbr.c

+2 −2
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ enum { 
	LBR_FORMAT_MAX_KNOWN    = LBR_FORMAT_TIME,

};



static enum {

static const enum {

	LBR_EIP_FLAGS		= 1,

	LBR_TSX			= 2,

} lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
@@ -287,7 +287,7 @@ inline u64 lbr_from_signext_quirk_wr(u64 val) 
/*

 * If quirk is needed, ensure sign extension is 61 bits:

 */

u64 lbr_from_signext_quirk_rd(u64 val)

static u64 lbr_from_signext_quirk_rd(u64 val)

{

	if (static_branch_unlikely(&lbr_from_quirk_key)) {

		/*

arch/x86/events/perf_event.h

+3 −0
Original line number Diff line number Diff line
@@ -562,6 +562,9 @@ struct x86_pmu { 
	ssize_t		(*events_sysfs_show)(char *page, u64 config);

	struct attribute **cpu_events;



	unsigned long	attr_freeze_on_smi;

	struct attribute **attrs;



	/*

	 * CPU Hotplug hooks

	 */

arch/x86/include/asm/msr-index.h

+2 −0
Original line number Diff line number Diff line
@@ -137,6 +137,8 @@ 
#define DEBUGCTLMSR_BTS_OFF_OS		(1UL <<  9)

#define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)

#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)

#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT	14

#define DEBUGCTLMSR_FREEZE_IN_SMM	(1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)



#define MSR_PEBS_FRONTEND		0x000003f7