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Commit 7445f432 authored by Indira Biruduraju's avatar Indira Biruduraju
Browse files

ARM: dts: msm: Add fmax support for holi GPU 

Add support for fmax of 875MHz, 650MHz, 430MHz
to holi GPU.

Change-Id: I9a2f607b68ca015ef4a02187f385834032323c40
parent b72b6430

qcom/holi-gpu.dtsi

+207 −75
Original line number Diff line number Diff line
@@ -37,6 +37,12 @@ msm_gpu: qcom,kgsl-3d0@5900000 { 
		qcom,min-access-length = <32>;

		qcom,ubwc-mode = <2>;



		/* Enable context aware freq. scaling */

		qcom,enable-ca-jump;



		/* Context aware jump busy penalty in us */

		qcom,ca-busy-penalty = <12000>;



		interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI>;

		interconnect-names = "gpu_icc_path";
@@ -83,12 +89,24 @@ msm_gpu: qcom,kgsl-3d0@5900000 { 
			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

		/*

		 * Speed-bin zero is default speed bin.

		 * For rest of the speed bins, speed-bin value

		 * is calulated as FMAX/4.8 MHz (round up to zero

		 * decimal places) + 2.

		 */

		qcom,gpu-pwrlevel-bins {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,gpu-pwrlevels";

			compatible = "qcom,gpu-pwrlevel-bins";



			qcom,gpu-pwrlevels-0 {

				#address-cells = <1>;

				#size-cells = <0>;

				qcom,speed-bin = <0>;

				qcom,ca-target-pwrlevel = <5>;

				qcom,initial-pwrlevel = <6>;



				/* TURBO_L1 */

				qcom,gpu-pwrlevel@0 {
@@ -170,7 +188,121 @@ msm_gpu: qcom,kgsl-3d0@5900000 { 
					qcom,bus-min-ddr7 = <1>;

					qcom,bus-max-ddr7 = <4>;

				};



			};



			qcom,gpu-pwrlevels-1 {

				#address-cells = <1>;

				#size-cells = <0>;

				qcom,speed-bin = <138>;

				qcom,ca-target-pwrlevel = <3>;

				qcom,initial-pwrlevel = <4>;



				/* NOM_L1 */

				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <650000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;



					qcom,bus-freq-ddr7 = <7>;

					qcom,bus-min-ddr7 = <5>;

					qcom,bus-max-ddr7 = <9>;



				};



				/* NOM */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <565000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;



					qcom,bus-freq-ddr7 = <6>;

					qcom,bus-min-ddr7 = <5>;

					qcom,bus-max-ddr7 = <8>;



				};



				/* SVS_L1 */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <430000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;



					qcom,bus-freq-ddr7 = <5>;

					qcom,bus-min-ddr7 = <4>;

					qcom,bus-max-ddr7 = <7>;



				};



				/* SVS */

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <355000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;



					qcom,bus-freq-ddr7 = <4>;

					qcom,bus-min-ddr7 = <2>;

					qcom,bus-max-ddr7= <5>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <253000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;



					qcom,bus-freq-ddr7 = <2>;

					qcom,bus-min-ddr7 = <1>;

					qcom,bus-max-ddr7 = <4>;

				};



			};



			qcom,gpu-pwrlevels-2 {

				#address-cells = <1>;

				#size-cells = <0>;

				qcom,speed-bin = <92>;

				qcom,ca-target-pwrlevel = <2>;

				qcom,initial-pwrlevel = <1>;



				/* SVS_L1 */

				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <430000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;



					qcom,bus-freq-ddr7 = <5>;

					qcom,bus-min-ddr7 = <4>;

					qcom,bus-max-ddr7 = <7>;



				};



				/* SVS */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <355000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;



					qcom,bus-freq-ddr7 = <4>;

					qcom,bus-min-ddr7 = <2>;

					qcom,bus-max-ddr7= <5>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <253000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;



					qcom,bus-freq-ddr7 = <2>;

					qcom,bus-min-ddr7 = <1>;

					qcom,bus-max-ddr7 = <4>;

				};



			};



		};



	 };



	kgsl_msm_iommu: qcom,kgsl-iommu@5940000 {