Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 741a26cf authored by Dillon Min's avatar Dillon Min Committed by Greg Kroah-Hartman
Browse files

clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system enter shell 

[ Upstream commit 6fc058a72f3b7b07fc4de6d66ad1f68951b00f6e ]

stm32's clk driver register two ltdc gate clk to clk core by
clk_hw_register_gate() and clk_hw_register_composite()

first: 'stm32f429_gates[]', clk name is 'ltdc', which no user to use.
second: 'stm32f429_aux_clk[]', clk name is 'lcd-tft', used by ltdc driver

both of them point to the same offset of stm32's RCC register. after
kernel enter console, clk core turn off ltdc's clk as 'stm32f429_gates[]'
is no one to use. but, actually 'stm32f429_aux_clk[]' is in use.

stm32f469/746/769 have the same issue, fix it.

Fixes: daf2d117 ("clk: stm32f4: Add lcd-tft clock")
Link: https://lore.kernel.org/linux-arm-kernel/1590564453-24499-7-git-send-email-dillon.minfei@gmail.com/
Link: https://lore.kernel.org/lkml/CAPTRvHkf0cK_4ZidM17rPo99gWDmxgqFt4CDUjqFFwkOeQeFDg@mail.gmail.com/


Signed-off-by: default avatarDillon Min <dillon.minfei@gmail.com>
Reviewed-by: default avatarPatrice Chotard <patrice.chotard@foss.st.com>
Acked-by: default avatarGabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/1635232282-3992-10-git-send-email-dillon.minfei@gmail.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 35d7be24

drivers/clk/clk-stm32f4.c

+0 −4
Original line number Original line Diff line number Diff line
@@ -129,7 +129,6 @@ static const struct stm32f4_gate_data stm32f429_gates[] __initconst = { 
	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },

};

};





static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {

static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
@@ -211,7 +210,6 @@ static const struct stm32f4_gate_data stm32f469_gates[] __initconst = { 
	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },

};

};





static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {

static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
@@ -286,7 +284,6 @@ static const struct stm32f4_gate_data stm32f746_gates[] __initconst = { 
	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 23,	"sai2",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 23,	"sai2",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },

};

};





static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {

static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {
@@ -364,7 +361,6 @@ static const struct stm32f4_gate_data stm32f769_gates[] __initconst = { 
	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 23,	"sai2",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 23,	"sai2",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 30,	"mdio",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 30,	"mdio",		"apb2_div" },

};

};