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Commit 73d7ec89 authored by Marc Gonzalez's avatar Marc Gonzalez Committed by Kishon Vijay Abraham I
Browse files

phy: qcom-qmp: Add msm8998 PCIe QMP PHY support 

Documentation for this PHY, and the proper configuration settings,
is *not* publicly available. Therefore the initialization sequence
is copied wholesale from downstream:

https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998-v2.dtsi?h=LE.UM.1.3.r3.25#n372



Reviewed-by: default avatarVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: default avatarMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 7e7b8ca6

drivers/phy/qualcomm/phy-qcom-qmp.c

+110 −0
Original line number Diff line number Diff line
@@ -242,6 +242,88 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),

};



static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),

};



static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),

};



static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),

};



static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),

};



static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
@@ -1149,6 +1231,31 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { 
	.no_pcs_sw_reset	= true,

};



static const struct qmp_phy_cfg msm8998_pciephy_cfg = {

	.type			= PHY_TYPE_PCIE,

	.nlanes			= 1,



	.serdes_tbl		= msm8998_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(msm8998_pcie_serdes_tbl),

	.tx_tbl			= msm8998_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(msm8998_pcie_tx_tbl),

	.rx_tbl			= msm8998_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(msm8998_pcie_rx_tbl),

	.pcs_tbl		= msm8998_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(msm8998_pcie_pcs_tbl),

	.clk_list		= msm8996_phy_clk_l,

	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),

	.reset_list		= ipq8074_pciephy_reset_l,

	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= pciephy_regs_layout,



	.start_ctrl             = SERDES_START | PCS_START,

	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.mask_com_pcs_ready	= PCS_READY,

};



static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {

	.type                   = PHY_TYPE_USB3,

	.nlanes                 = 1,
@@ -1870,6 +1977,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { 
	}, {

		.compatible = "qcom,msm8996-qmp-usb3-phy",

		.data = &msm8996_usb3phy_cfg,

	}, {

		.compatible = "qcom,msm8998-qmp-pcie-phy",

		.data = &msm8998_pciephy_cfg,

	}, {

		.compatible = "qcom,msm8998-qmp-ufs-phy",

		.data = &sdm845_ufsphy_cfg,

drivers/phy/qualcomm/phy-qcom-qmp.h

+12 −0
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ 
#define QSERDES_V3_RX_RX_BAND				0x110

#define QSERDES_V3_RX_RX_INTERFACE_MODE			0x11c

#define QSERDES_V3_RX_RX_MODE_00			0x164

#define QSERDES_V3_RX_RX_MODE_01			0x168



/* Only for QMP V3 PHY - PCS registers */

#define QPHY_V3_PCS_POWER_DOWN_CONTROL			0x004
@@ -280,6 +281,7 @@ 
#define QPHY_V3_PCS_TSYNC_RSYNC_TIME			0x08c

#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x0a0

#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK		0x0a4

#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME		0x0a8

#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK		0x0b0

#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME		0x0b8

#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME		0x0bc
@@ -292,13 +294,23 @@ 
#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME			0x138

#define QPHY_V3_PCS_RX_SIGDET_CTRL1			0x13c

#define QPHY_V3_PCS_RX_SIGDET_CTRL2			0x140

#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB	0x1a8

#define QPHY_V3_PCS_OSC_DTCT_ACTIONS			0x1ac

#define QPHY_V3_PCS_SIGDET_CNTRL			0x1b0

#define QPHY_V3_PCS_TX_MID_TERM_CTRL1			0x1bc

#define QPHY_V3_PCS_MULTI_LANE_CTRL1			0x1c4

#define QPHY_V3_PCS_RX_SIGDET_LVL			0x1d8

#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB	0x1dc

#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB	0x1e0

#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1			0x20c

#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2			0x210



/* Only for QMP V3 PHY - PCS_MISC registers */

#define QPHY_V3_PCS_MISC_CLAMP_ENABLE			0x0c

#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2		0x2c

#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1	0x44

#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2		0x54

#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4		0x5c

#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5		0x60



#endif