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Commit 73acc7df authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload handlers 



MIPS R2 documents state that an execution hazard barrier is needed
after a TLBR before reading EntryLo.

Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5526/
parent b90b3802

arch/mips/mm/tlbex.c

+26 −0
Original line number Diff line number Diff line
@@ -1935,6 +1935,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void) 
		uasm_i_nop(&p);



		uasm_i_tlbr(&p);



		switch (current_cpu_type()) {

		default:

			if (cpu_has_mips_r2) {

				uasm_i_ehb(&p);



		case CPU_CAVIUM_OCTEON:

		case CPU_CAVIUM_OCTEON_PLUS:

		case CPU_CAVIUM_OCTEON2:

				break;

			}

		}



		/* Examine  entrylo 0 or 1 based on ptr. */

		if (use_bbit_insns()) {

			uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
@@ -1989,6 +2002,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void) 
		uasm_i_nop(&p);



		uasm_i_tlbr(&p);



		switch (current_cpu_type()) {

		default:

			if (cpu_has_mips_r2) {

				uasm_i_ehb(&p);



		case CPU_CAVIUM_OCTEON:

		case CPU_CAVIUM_OCTEON_PLUS:

		case CPU_CAVIUM_OCTEON2:

				break;

			}

		}



		/* Examine  entrylo 0 or 1 based on ptr. */

		if (use_bbit_insns()) {

			uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);