Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 73872733 authored by Dave Olson's avatar Dave Olson Committed by Roland Dreier
Browse files

IB/ipath: Remove unused MDIO interface code 



This code has been unused for some time, but still had leftovers
from when it was used.

Signed-off-by: default avatarDave Olson <dave.olson@qlogic.com>
Signed-off-by: default avatarRoland Dreier <rolandd@cisco.com>
parent 2ec8e662

drivers/infiniband/hw/ipath/ipath_driver.c

+0 −71
Original line number Diff line number Diff line
@@ -1618,77 +1618,6 @@ int ipath_create_rcvhdrq(struct ipath_devdata *dd, 
	return ret;

}



int ipath_waitfor_complete(struct ipath_devdata *dd, ipath_kreg reg_id,

			   u64 bits_to_wait_for, u64 * valp)

{

	unsigned long timeout;

	u64 lastval, val;

	int ret;



	lastval = ipath_read_kreg64(dd, reg_id);

	/* wait a ridiculously long time */

	timeout = jiffies + msecs_to_jiffies(5);

	do {

		val = ipath_read_kreg64(dd, reg_id);

		/* set so they have something, even on failures. */

		*valp = val;

		if ((val & bits_to_wait_for) == bits_to_wait_for) {

			ret = 0;

			break;

		}

		if (val != lastval)

			ipath_cdbg(VERBOSE, "Changed from %llx to %llx, "

				   "waiting for %llx bits\n",

				   (unsigned long long) lastval,

				   (unsigned long long) val,

				   (unsigned long long) bits_to_wait_for);

		cond_resched();

		if (time_after(jiffies, timeout)) {

			ipath_dbg("Didn't get bits %llx in register 0x%x, "

				  "got %llx\n",

				  (unsigned long long) bits_to_wait_for,

				  reg_id, (unsigned long long) *valp);

			ret = -ENODEV;

			break;

		}

	} while (1);



	return ret;

}



/**

 * ipath_waitfor_mdio_cmdready - wait for last command to complete

 * @dd: the infinipath device

 *

 * Like ipath_waitfor_complete(), but we wait for the CMDVALID bit to go

 * away indicating the last command has completed.  It doesn't return data

 */

int ipath_waitfor_mdio_cmdready(struct ipath_devdata *dd)

{

	unsigned long timeout;

	u64 val;

	int ret;



	/* wait a ridiculously long time */

	timeout = jiffies + msecs_to_jiffies(5);

	do {

		val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_mdio);

		if (!(val & IPATH_MDIO_CMDVALID)) {

			ret = 0;

			break;

		}

		cond_resched();

		if (time_after(jiffies, timeout)) {

			ipath_dbg("CMDVALID stuck in mdio reg? (%llx)\n",

				  (unsigned long long) val);

			ret = -ENODEV;

			break;

		}

	} while (1);



	return ret;

}





/*

 * Flush all sends that might be in the ready to send state, as well as any

drivers/infiniband/hw/ipath/ipath_iba6110.c

+1 −27
Original line number Diff line number Diff line
@@ -1274,8 +1274,7 @@ static void ipath_ht_init_hwerrors(struct ipath_devdata *dd) 
	val &= ~INFINIPATH_HWE_HTCMISCERR4;



	/*

	 * PLL ignored because MDIO interface has a logic problem

	 * for reads, on Comstock and Ponderosa.  BRINGUP

	 * PLL ignored because unused MDIO interface has a logic problem

	 */

	if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)

		val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
@@ -1353,16 +1352,6 @@ static int ipath_ht_bringup_serdes(struct ipath_devdata *dd) 
	}



	val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);

	if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &

	     INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {

		val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<

			 INFINIPATH_XGXS_MDIOADDR_SHIFT);

		/*

		 * we use address 3

		 */

		val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;

		change = 1;

	}

	if (val & INFINIPATH_XGXS_RESET) {

		/* normally true after boot */

		val &= ~INFINIPATH_XGXS_RESET;
@@ -1398,21 +1387,6 @@ static int ipath_ht_bringup_serdes(struct ipath_devdata *dd) 
		   (unsigned long long)

		   ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));



	if (!ipath_waitfor_mdio_cmdready(dd)) {

		ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,

				 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,

						IPATH_MDIO_CTRL_XGXS_REG_8,

						0));

		if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,

					   IPATH_MDIO_DATAVALID, &val))

			ipath_dbg("Never got MDIO data for XGXS status "

				  "read\n");

		else

			ipath_cdbg(VERBOSE, "MDIO Read reg8, "

				   "'bank' 31 %x\n", (u32) val);

	} else

		ipath_dbg("Never got MDIO cmdready for XGXS status read\n");



	return ret;		/* for now, say we always succeeded */

}

drivers/infiniband/hw/ipath/ipath_iba6120.c

+1 −25
Original line number Diff line number Diff line
@@ -725,17 +725,8 @@ static int ipath_pe_bringup_serdes(struct ipath_devdata *dd) 


	val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);

	prev_val = val;

	if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &

	     INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {

		val &=

			~(INFINIPATH_XGXS_MDIOADDR_MASK <<

			  INFINIPATH_XGXS_MDIOADDR_SHIFT);

		/* MDIO address 3 */

		val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;

	}

	if (val & INFINIPATH_XGXS_RESET) {

	if (val & INFINIPATH_XGXS_RESET)

		val &= ~INFINIPATH_XGXS_RESET;

	}

	if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &

	     INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {

		/* need to compensate for Tx inversion in partner */
@@ -765,21 +756,6 @@ static int ipath_pe_bringup_serdes(struct ipath_devdata *dd) 
		   (unsigned long long)

		   ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));



	if (!ipath_waitfor_mdio_cmdready(dd)) {

		ipath_write_kreg(

			dd, dd->ipath_kregs->kr_mdio,

			ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,

				       IPATH_MDIO_CTRL_XGXS_REG_8, 0));

		if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,

					   IPATH_MDIO_DATAVALID, &val))

			ipath_dbg("Never got MDIO data for XGXS "

				  "status read\n");

		else

			ipath_cdbg(VERBOSE, "MDIO Read reg8, "

				   "'bank' 31 %x\n", (u32) val);

	} else

		ipath_dbg("Never got MDIO cmdready for XGXS status read\n");



	return ret;

}

drivers/infiniband/hw/ipath/ipath_kernel.h

+0 −29
Original line number Diff line number Diff line
@@ -777,8 +777,6 @@ int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv); 


/* free up any allocated data at closes */

void ipath_free_data(struct ipath_portdata *dd);

int ipath_waitfor_mdio_cmdready(struct ipath_devdata *);

int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *);

u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *);

void ipath_init_iba6120_funcs(struct ipath_devdata *);

void ipath_init_iba6110_funcs(struct ipath_devdata *);
@@ -802,33 +800,6 @@ void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val); 
 */

#define IPATH_DFLT_RCVHDRSIZE 9



#define IPATH_MDIO_CMD_WRITE   1

#define IPATH_MDIO_CMD_READ    2

#define IPATH_MDIO_CLD_DIV     25	/* to get 2.5 Mhz mdio clock */

#define IPATH_MDIO_CMDVALID    0x40000000	/* bit 30 */

#define IPATH_MDIO_DATAVALID   0x80000000	/* bit 31 */

#define IPATH_MDIO_CTRL_STD    0x0



static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data)

{

	return (((u64) IPATH_MDIO_CLD_DIV) << 32) |

		(cmd << 26) |

		(dev << 21) |

		(reg << 16) |

		(data & 0xFFFF);

}



		/* signal and fifo status, in bank 31 */

#define IPATH_MDIO_CTRL_XGXS_REG_8  0x8

		/* controls loopback, redundancy */

#define IPATH_MDIO_CTRL_8355_REG_1  0x10

		/* premph, encdec, etc. */

#define IPATH_MDIO_CTRL_8355_REG_2  0x11

		/* Kchars, etc. */

#define IPATH_MDIO_CTRL_8355_REG_6  0x15

#define IPATH_MDIO_CTRL_8355_REG_9  0x18

#define IPATH_MDIO_CTRL_8355_REG_10 0x1D



int ipath_get_user_pages(unsigned long, size_t, struct page **);

void ipath_release_user_pages(struct page **, size_t);

void ipath_release_user_pages_on_close(struct page **, size_t);

drivers/infiniband/hw/ipath/ipath_registers.h

+0 −16
Original line number Diff line number Diff line
@@ -271,20 +271,6 @@ 
#define INFINIPATH_EXTC_LEDGBLOK_ON          0x00000002ULL

#define INFINIPATH_EXTC_LEDGBLERR_OFF        0x00000001ULL



/* kr_mdio bits */

#define INFINIPATH_MDIO_CLKDIV_MASK 0x7FULL

#define INFINIPATH_MDIO_CLKDIV_SHIFT 32

#define INFINIPATH_MDIO_COMMAND_MASK 0x7ULL

#define INFINIPATH_MDIO_COMMAND_SHIFT 26

#define INFINIPATH_MDIO_DEVADDR_MASK 0x1FULL

#define INFINIPATH_MDIO_DEVADDR_SHIFT 21

#define INFINIPATH_MDIO_REGADDR_MASK 0x1FULL

#define INFINIPATH_MDIO_REGADDR_SHIFT 16

#define INFINIPATH_MDIO_DATA_MASK 0xFFFFULL

#define INFINIPATH_MDIO_DATA_SHIFT 0

#define INFINIPATH_MDIO_CMDVALID    0x0000000040000000ULL

#define INFINIPATH_MDIO_RDDATAVALID 0x0000000080000000ULL



/* kr_partitionkey bits */

#define INFINIPATH_PKEY_SIZE 16

#define INFINIPATH_PKEY_MASK 0xFFFF
@@ -302,8 +288,6 @@ 


/* kr_xgxsconfig bits */

#define INFINIPATH_XGXS_RESET          0x7ULL

#define INFINIPATH_XGXS_MDIOADDR_MASK  0xfULL

#define INFINIPATH_XGXS_MDIOADDR_SHIFT 4

#define INFINIPATH_XGXS_RX_POL_SHIFT 19

#define INFINIPATH_XGXS_RX_POL_MASK 0xfULL