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Commit 735ee005 authored by Guo Ren's avatar Guo Ren
Browse files

csky: Misc headers 



This patch adds csky registers' definition, bitops, byteorder,
asm-offsets codes.

Signed-off-by: default avatarGuo Ren <ren_guo@c-sky.com>
Reviewed-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 99106986

arch/csky/abiv1/inc/abi/reg_ops.h

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/* SPDX-License-Identifier: GPL-2.0 */

// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.



#ifndef __ABI_REG_OPS_H

#define __ABI_REG_OPS_H

#include <asm/reg_ops.h>



#define cprcr(reg)					\

({							\

	unsigned int tmp;				\

	asm volatile("cprcr %0, "reg"\n":"=b"(tmp));	\

	tmp;						\

})



#define cpwcr(reg, val)					\

({							\

	asm volatile("cpwcr %0, "reg"\n"::"b"(val));	\

})



static inline unsigned int mfcr_hint(void)

{

	return mfcr("cr30");

}



static inline unsigned int mfcr_ccr2(void) { return 0; }



#endif /* __ABI_REG_OPS_H */

arch/csky/abiv1/inc/abi/regdef.h

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/* SPDX-License-Identifier: GPL-2.0 */

// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.



#ifndef __ASM_CSKY_REGDEF_H

#define __ASM_CSKY_REGDEF_H



#define syscallid	r1

#define r11_sig		r11



#define regs_syscallid(regs) regs->regs[9]



/*

 * PSR format:

 * | 31 | 30-24 | 23-16 | 15 14 | 13-0 |

 *   S     CPID     VEC     TM

 *

 *    S: Super Mode

 * CPID: Coprocessor id, only 15 for MMU

 *  VEC: Exception Number

 *   TM: Trace Mode

 */

#define DEFAULT_PSR_VALUE	0x8f000000



#define SYSTRACE_SAVENUM	2



#endif /* __ASM_CSKY_REGDEF_H */

arch/csky/abiv2/inc/abi/reg_ops.h

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/* SPDX-License-Identifier: GPL-2.0 */

// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.



#ifndef __ABI_REG_OPS_H

#define __ABI_REG_OPS_H

#include <asm/reg_ops.h>



static inline unsigned int mfcr_hint(void)

{

	return mfcr("cr31");

}



static inline unsigned int mfcr_ccr2(void)

{

	return mfcr("cr23");

}

#endif /* __ABI_REG_OPS_H */

arch/csky/abiv2/inc/abi/regdef.h

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/* SPDX-License-Identifier: GPL-2.0 */

// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.



#ifndef __ASM_CSKY_REGDEF_H

#define __ASM_CSKY_REGDEF_H



#define syscallid	r7

#define r11_sig		r11



#define regs_syscallid(regs) regs->regs[3]



/*

 * PSR format:

 * | 31 | 30-24 | 23-16 | 15 14 | 13-10 | 9 | 8-0 |

 *   S              VEC     TM            MM

 *

 *   S: Super Mode

 * VEC: Exception Number

 *  TM: Trace Mode

 *  MM: Memory unaligned addr access

 */

#define DEFAULT_PSR_VALUE	0x80000200



#define SYSTRACE_SAVENUM	5



#endif /* __ASM_CSKY_REGDEF_H */

arch/csky/include/asm/bitops.h

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/* SPDX-License-Identifier: GPL-2.0 */

// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.



#ifndef __ASM_CSKY_BITOPS_H

#define __ASM_CSKY_BITOPS_H



#include <linux/compiler.h>

#include <asm/barrier.h>



/*

 * asm-generic/bitops/ffs.h

 */

static inline int ffs(int x)

{

	if (!x)

		return 0;



	asm volatile (

		"brev %0\n"

		"ff1  %0\n"

		"addi %0, 1\n"

		: "=&r"(x)

		: "0"(x));

	return x;

}



/*

 * asm-generic/bitops/__ffs.h

 */

static __always_inline unsigned long __ffs(unsigned long x)

{

	asm volatile (

		"brev %0\n"

		"ff1  %0\n"

		: "=&r"(x)

		: "0"(x));

	return x;

}



/*

 * asm-generic/bitops/fls.h

 */

static __always_inline int fls(int x)

{

	asm volatile(

		"ff1 %0\n"

		: "=&r"(x)

		: "0"(x));



	return (32 - x);

}



/*

 * asm-generic/bitops/__fls.h

 */

static __always_inline unsigned long __fls(unsigned long x)

{

	return fls(x) - 1;

}



#include <asm-generic/bitops/ffz.h>

#include <asm-generic/bitops/fls64.h>

#include <asm-generic/bitops/find.h>



#ifndef _LINUX_BITOPS_H

#error only <linux/bitops.h> can be included directly

#endif



#include <asm-generic/bitops/sched.h>

#include <asm-generic/bitops/hweight.h>

#include <asm-generic/bitops/lock.h>

#include <asm-generic/bitops/atomic.h>



/*

 * bug fix, why only could use atomic!!!!

 */

#include <asm-generic/bitops/non-atomic.h>

#define __clear_bit(nr, vaddr) clear_bit(nr, vaddr)



#include <asm-generic/bitops/le.h>

#include <asm-generic/bitops/ext2-atomic.h>

#endif /* __ASM_CSKY_BITOPS_H */