Loading qcom/yupik-rumi.dtsi +5 −1 Original line number Diff line number Diff line Loading @@ -167,7 +167,11 @@ }; &gcc { clocks = <&bi_tcxo>, <&sleep_clk>; clocks = <&bi_tcxo>, <&sleep_clk>, <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; }; &gpucc { Loading qcom/yupik.dtsi +10 −2 Original line number Diff line number Diff line Loading @@ -720,8 +720,16 @@ reg = <0x100000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; clock-names = "bi_tcxo", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; }; Loading Loading
qcom/yupik-rumi.dtsi +5 −1 Original line number Diff line number Diff line Loading @@ -167,7 +167,11 @@ }; &gcc { clocks = <&bi_tcxo>, <&sleep_clk>; clocks = <&bi_tcxo>, <&sleep_clk>, <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; }; &gpucc { Loading
qcom/yupik.dtsi +10 −2 Original line number Diff line number Diff line Loading @@ -720,8 +720,16 @@ reg = <0x100000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; clock-names = "bi_tcxo", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; }; Loading