Loading qcom/yupik-hsp.dtsi +23 −0 Original line number Diff line number Diff line #include "yupik.dtsi" / { }; &gcc { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>; clock-names = "bi_tcxo", "sleep_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk"; /delete-property/ protected-clocks; }; &gcc_pcie_0_gdsc { status = "ok"; }; &gcc_pcie_1_gdsc { status = "ok"; }; &gcc_usb30_sec_gdsc { status = "ok"; }; qcom/yupik-idp-hsp-overlay.dts +1 −0 Original line number Diff line number Diff line /dts-v1/; /plugin/; #include <dt-bindings/interconnect/qcom,yupik.h> #include "yupik-idp-hsp.dtsi" / { Loading qcom/yupik-idp-hsp.dtsi +62 −0 Original line number Diff line number Diff line #include "yupik-idp.dtsi" #include "qcx6490-cnss.dtsi" &wlan { qcom,same-dt-multi-dev; }; &pcie0 { status = "ok"; }; &pcie0_msi { status = "ok"; }; &pcie1 { status = "ok"; qcom,boot-option = <0x0>; qcom,ep-gpio = <&tlmm 19 0>; pinctrl-0 = <&pcie1_perst_default &pcie1_clkreq_default &pcie1_wake_default &pcie1_ep_default>; pinctrl-1 = <&pcie1_perst_default &pcie1_clkreq_sleep &pcie1_wake_default &pcie1_ep_default>; }; &pcie1_msi { status = "ok"; }; &pm7325_gpios { usb2_vbus_boost { usb2_vbus_boost_default: usb2_vbus_boost_default { pins = "gpio8"; function = "normal"; output-low; power-source = <0>; /* 1.8V input supply */ }; }; }; &soc { usb2_vbus_boost_reg: usb2_vbus_boost_reg { compatible = "regulator-fixed"; regulator-name = "usb2_vbus_boost_vreg"; startup-delay-us = <4000>; enable-active-high; gpios = <&pm7325_gpios 8 0>; pinctrl-names = "default"; pinctrl-0 = <&usb2_vbus_boost_default>; }; }; &usb1 { vbus_dwc3-supply = <&usb2_vbus_boost_reg>; qcom,default-mode-none; status = "ok"; }; &usb2_phy1 { status = "ok"; }; qcom/yupikp-idp-hsp-overlay.dts +1 −0 Original line number Diff line number Diff line /dts-v1/; /plugin/; #include <dt-bindings/interconnect/qcom,yupik.h> #include "yupikp-idp-hsp.dtsi" / { Loading Loading
qcom/yupik-hsp.dtsi +23 −0 Original line number Diff line number Diff line #include "yupik.dtsi" / { }; &gcc { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>; clock-names = "bi_tcxo", "sleep_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk"; /delete-property/ protected-clocks; }; &gcc_pcie_0_gdsc { status = "ok"; }; &gcc_pcie_1_gdsc { status = "ok"; }; &gcc_usb30_sec_gdsc { status = "ok"; };
qcom/yupik-idp-hsp-overlay.dts +1 −0 Original line number Diff line number Diff line /dts-v1/; /plugin/; #include <dt-bindings/interconnect/qcom,yupik.h> #include "yupik-idp-hsp.dtsi" / { Loading
qcom/yupik-idp-hsp.dtsi +62 −0 Original line number Diff line number Diff line #include "yupik-idp.dtsi" #include "qcx6490-cnss.dtsi" &wlan { qcom,same-dt-multi-dev; }; &pcie0 { status = "ok"; }; &pcie0_msi { status = "ok"; }; &pcie1 { status = "ok"; qcom,boot-option = <0x0>; qcom,ep-gpio = <&tlmm 19 0>; pinctrl-0 = <&pcie1_perst_default &pcie1_clkreq_default &pcie1_wake_default &pcie1_ep_default>; pinctrl-1 = <&pcie1_perst_default &pcie1_clkreq_sleep &pcie1_wake_default &pcie1_ep_default>; }; &pcie1_msi { status = "ok"; }; &pm7325_gpios { usb2_vbus_boost { usb2_vbus_boost_default: usb2_vbus_boost_default { pins = "gpio8"; function = "normal"; output-low; power-source = <0>; /* 1.8V input supply */ }; }; }; &soc { usb2_vbus_boost_reg: usb2_vbus_boost_reg { compatible = "regulator-fixed"; regulator-name = "usb2_vbus_boost_vreg"; startup-delay-us = <4000>; enable-active-high; gpios = <&pm7325_gpios 8 0>; pinctrl-names = "default"; pinctrl-0 = <&usb2_vbus_boost_default>; }; }; &usb1 { vbus_dwc3-supply = <&usb2_vbus_boost_reg>; qcom,default-mode-none; status = "ok"; }; &usb2_phy1 { status = "ok"; };
qcom/yupikp-idp-hsp-overlay.dts +1 −0 Original line number Diff line number Diff line /dts-v1/; /plugin/; #include <dt-bindings/interconnect/qcom,yupik.h> #include "yupikp-idp-hsp.dtsi" / { Loading