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Commit 71eec083 authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov
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Documentation: dt: edac: Add Stratix10 Peripheral bindings 



Add peripheral bindings for Stratix10 EDAC to capture
the differences between the ARM64 and ARM32 architecture.

Signed-off-by: default avatarThor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mark.rutland@arm.com
Cc: mchehab@kernel.org
Link: https://lkml.kernel.org/r/1554388597-28019-3-git-send-email-thor.thayer@linux.intel.com
parent b9c8172e

Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt

+106 −0
Original line number Original line Diff line number Diff line
@@ -258,6 +258,49 @@ Required Properties: 
- compatible : Should be "altr,sdram-edac-s10"

- compatible : Should be "altr,sdram-edac-s10"

- interrupts : Should be single bit error interrupt.

- interrupts : Should be single bit error interrupt.





On-Chip RAM ECC

Required Properties:

- compatible      : Should be "altr,socfpga-s10-ocram-ecc"

- reg             : Address and size for ECC block registers.

- altr,ecc-parent : phandle to parent OCRAM node.

- interrupts      : Should be single bit error interrupt.



Ethernet FIFO ECC

Required Properties:

- compatible      : Should be "altr,socfpga-s10-eth-mac-ecc"

- reg             : Address and size for ECC block registers.

- altr,ecc-parent : phandle to parent Ethernet node.

- interrupts      : Should be single bit error interrupt.



NAND FIFO ECC

Required Properties:

- compatible      : Should be "altr,socfpga-s10-nand-ecc"

- reg             : Address and size for ECC block registers.

- altr,ecc-parent : phandle to parent NAND node.

- interrupts      : Should be single bit error interrupt.



DMA FIFO ECC

Required Properties:

- compatible      : Should be "altr,socfpga-s10-dma-ecc"

- reg             : Address and size for ECC block registers.

- altr,ecc-parent : phandle to parent DMA node.

- interrupts      : Should be single bit error interrupt.



USB FIFO ECC

Required Properties:

- compatible      : Should be "altr,socfpga-s10-usb-ecc"

- reg             : Address and size for ECC block registers.

- altr,ecc-parent : phandle to parent USB node.

- interrupts      : Should be single bit error interrupt.



SDMMC FIFO ECC

Required Properties:

- compatible      : Should be "altr,socfpga-s10-sdmmc-ecc"

- reg             : Address and size for ECC block registers.

- altr,ecc-parent : phandle to parent SD/MMC node.

- interrupts      : Should be single bit error interrupt for port A

		    and then single bit error interrupt for port B.



Example:

Example:





	eccmgr {

	eccmgr {
@@ -274,4 +317,67 @@ Example: 
			compatible = "altr,sdram-edac-s10";

			compatible = "altr,sdram-edac-s10";

			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;

		};

		};



		ocram-ecc@ff8cc000 {

			compatible = "altr,socfpga-s10-ocram-ecc";

			reg = <ff8cc000 0x100>;

			altr,ecc-parent = <&ocram>;

			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;

		};



		emac0-rx-ecc@ff8c0000 {

			compatible = "altr,socfpga-s10-eth-mac-ecc";

			reg = <0xff8c0000 0x100>;

			altr,ecc-parent = <&gmac0>;

			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

		};



		emac0-tx-ecc@ff8c0400 {

			compatible = "altr,socfpga-s10-eth-mac-ecc";

			reg = <0xff8c0400 0x100>;

			altr,ecc-parent = <&gmac0>;

			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'

		};



		nand-buf-ecc@ff8c8000 {

			compatible = "altr,socfpga-s10-nand-ecc";

			reg = <0xff8c8000 0x100>;

			altr,ecc-parent = <&nand>;

			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;

		};



		nand-rd-ecc@ff8c8400 {

			compatible = "altr,socfpga-s10-nand-ecc";

			reg = <0xff8c8400 0x100>;

			altr,ecc-parent = <&nand>;

			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;

		};



		nand-wr-ecc@ff8c8800 {

			compatible = "altr,socfpga-s10-nand-ecc";

			reg = <0xff8c8800 0x100>;

			altr,ecc-parent = <&nand>;

			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;

		};



		dma-ecc@ff8c9000 {

			compatible = "altr,socfpga-s10-dma-ecc";

			reg = <0xff8c9000 0x100>;

			altr,ecc-parent = <&pdma>;

			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;



		usb0-ecc@ff8c4000 {

			compatible = "altr,socfpga-s10-usb-ecc";

			reg = <0xff8c4000 0x100>;

			altr,ecc-parent = <&usb0>;

			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;

		};



		sdmmc-ecc@ff8c8c00 {

			compatible = "altr,socfpga-s10-sdmmc-ecc";

			reg = <0xff8c8c00 0x100>;

			altr,ecc-parent = <&mmc>;

			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,

				     <15 IRQ_TYPE_LEVEL_HIGH>;

		};

	};
 
	};