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Commit 71d4d5cb authored by Harshdeep Dhatt's avatar Harshdeep Dhatt Committed by Jordan Crouse
Browse files

msm: kgsl: bus dcvs fixes 



Remove the unused bus.mod member and make the bus governor compile in the
new directory structure.

Change-Id: I8c9bf21bb3b260cc932e1a0e1835788905cd67b5
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent cac5edff

drivers/gpu/msm/governor_gpubw_mon.c

+11 −7
Original line number Diff line number Diff line
@@ -5,11 +5,11 @@ 


#include <linux/devfreq.h>

#include <linux/module.h>

#include <linux/msm_adreno_devfreq.h>

#include <linux/slab.h>



#include "devfreq_trace.h"

#include "governor.h"

#include "../../devfreq/governor.h"

#include "msm_adreno_devfreq.h"



#define MIN_BUSY                1000

#define LONG_FLOOR              50000
@@ -95,7 +95,7 @@ static int devfreq_gpubw_get_target(struct devfreq *df, 
	} else {

		/* GPU votes for IB not AB so don't under vote the system */

		norm_cycles = (100 * norm_cycles) / TARGET;

		act_level = b.buslevel + b.mod;

		act_level = b.buslevel;

		act_level = (act_level < 0) ? 0 : act_level;

		act_level = (act_level >= priv->bus.num) ?

		(priv->bus.num - 1) : act_level;
@@ -157,16 +157,20 @@ static int gpubw_start(struct devfreq *devfreq) 


	/* Set up the cut-over percentages for the bus calculation. */

	for (i = 0; i < priv->bus.num; i++) {

		t1 = (u32)(100 * priv->bus.ib[i]) /

				(u32)priv->bus.ib[priv->bus.num - 1];

		t1 = (u32)(100 * priv->bus.ib_kbps[i]) /

				(u32)priv->bus.ib_kbps[priv->bus.num - 1];

		priv->bus.p_up[i] = t1 - HIST;

		priv->bus.p_down[i] = t2 - 2 * HIST;

		t2 = t1;

	}

	/* Set the upper-most and lower-most bounds correctly. */

	priv->bus.p_down[0] = 0;

	priv->bus.p_down[1] = (priv->bus.p_down[1] > (2 * HIST)) ?

				priv->bus.p_down[1] : (2 * HIST);



	for (i = 0; i < priv->bus.num; i++) {

		if (priv->bus.p_down[i] < 2 * HIST)

			priv->bus.p_down[i] = 2 * HIST;

	}



	if (priv->bus.num >= 1)

		priv->bus.p_up[priv->bus.num - 1] = 100;

	_update_cutoff(priv, priv->bus.max);

drivers/gpu/msm/governor_msm_adreno_tz.c

+15 −11
Original line number Diff line number Diff line
@@ -5,17 +5,19 @@ 
#include <linux/errno.h>

#include <linux/module.h>

#include <linux/devfreq.h>

#include <linux/dma-mapping.h>

#include <linux/math64.h>

#include <linux/spinlock.h>

#include <linux/slab.h>

#include <linux/io.h>

#include <linux/ftrace.h>

#include <linux/mm.h>

#include <linux/msm_adreno_devfreq.h>

#include <linux/qcom_scm.h>

#include <asm/cacheflush.h>

#include <soc/qcom/qtee_shmbridge.h>

#include "governor.h"

#include <linux/qtee_shmbridge.h>



#include "../../devfreq/governor.h"

#include "msm_adreno_devfreq.h"



static DEFINE_SPINLOCK(tz_lock);

static DEFINE_SPINLOCK(sample_lock);
@@ -197,7 +199,8 @@ static int __secure_tz_update_entry3(int level, s64 total_time, s64 busy_time, 
	return ret;

}



static int tz_init_ca(struct devfreq_msm_adreno_tz_data *priv)

static int tz_init_ca(struct device *dev,

	struct devfreq_msm_adreno_tz_data *priv)

{

	unsigned int tz_ca_data[2];

	phys_addr_t paddr;
@@ -226,8 +229,8 @@ static int tz_init_ca(struct devfreq_msm_adreno_tz_data *priv) 
	memcpy(tz_buf, tz_ca_data, sizeof(tz_ca_data));

	/* Ensure memcpy completes execution */

	mb();

	dmac_flush_range(tz_buf,

		tz_buf + PAGE_ALIGN(sizeof(tz_ca_data)));

	dma_sync_single_for_device(dev, paddr,

		PAGE_ALIGN(sizeof(tz_ca_data)), DMA_BIDIRECTIONAL);



	ret = qcom_scm_dcvs_init_ca_v2(paddr, sizeof(tz_ca_data));
@@ -239,7 +242,7 @@ static int tz_init_ca(struct devfreq_msm_adreno_tz_data *priv) 
	return ret;

}



static int tz_init(struct devfreq_msm_adreno_tz_data *priv,

static int tz_init(struct device *dev, struct devfreq_msm_adreno_tz_data *priv,

			unsigned int *tz_pwrlevels, u32 size_pwrlevels,

			unsigned int *version, u32 size_version)

{
@@ -268,7 +271,8 @@ static int tz_init(struct devfreq_msm_adreno_tz_data *priv, 
		memcpy(tz_buf, tz_pwrlevels, size_pwrlevels);

		/* Ensure memcpy completes execution */

		mb();

		dmac_flush_range(tz_buf, tz_buf + PAGE_ALIGN(size_pwrlevels));

		dma_sync_single_for_device(dev, paddr,

			PAGE_ALIGN(size_pwrlevels), DMA_BIDIRECTIONAL);



		ret = qcom_scm_dcvs_init_v2(paddr, size_pwrlevels, version);

		if (!ret)
@@ -283,7 +287,7 @@ static int tz_init(struct devfreq_msm_adreno_tz_data *priv, 
	 /* Initialize context aware feature, if enabled. */

	if (!ret && priv->ctxt_aware_enable) {

		if (priv->is_64 && qcom_scm_dcvs_ca_available()) {

			ret = tz_init_ca(priv);

			ret = tz_init_ca(dev, priv);

			/*

			 * If context aware feature initialization fails,

			 * just print an error message and return
@@ -455,8 +459,8 @@ static int tz_start(struct devfreq *devfreq) 
	INIT_WORK(&gpu_profile->partner_resume_event_ws,

					do_partner_resume_event);



	ret = tz_init(priv, tz_pwrlevels, sizeof(tz_pwrlevels), &version,

				sizeof(version));

	ret = tz_init(&devfreq->dev, priv, tz_pwrlevels, sizeof(tz_pwrlevels),

			&version, sizeof(version));

	if (ret != 0 || version > MAX_TZ_VERSION) {

		pr_err(TAG "tz_init failed\n");

		return ret;

drivers/gpu/msm/kgsl_pwrscale.c

+0 −1
Original line number Diff line number Diff line
@@ -390,7 +390,6 @@ int kgsl_devfreq_get_dev_status(struct device *dev, 


		last_b->ram_time = device->pwrscale.accum_stats.ram_time;

		last_b->ram_wait = device->pwrscale.accum_stats.ram_wait;

		last_b->mod = device->pwrctrl.bus_mod;

		last_b->buslevel = device->pwrctrl.cur_buslevel;

	}

drivers/gpu/msm/msm_adreno_devfreq.h

+0 −1
Original line number Diff line number Diff line
@@ -31,7 +31,6 @@ int kgsl_devfreq_del_notifier(struct device *device, 
struct xstats {

	u64 ram_time;

	u64 ram_wait;

	int mod;

	int buslevel;

};