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Commit 71c5574f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add dmips and dynamic power co-efficient for Yupik"

parents 337876c4 66008f5a

qcom/yupik.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -63,6 +63,8 @@ 
			reg = <0x0 0x0>;

			enable-method = "psci";

			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";
@@ -82,6 +84,8 @@ 
			reg = <0x0 0x100>;

			enable-method = "psci";

			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";
@@ -96,6 +100,8 @@ 
			reg = <0x0 0x200>;

			enable-method = "psci";

			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_2>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";
@@ -110,6 +116,8 @@ 
			reg = <0x0 0x300>;

			enable-method = "psci";

			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_3>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";
@@ -124,6 +132,8 @@ 
			reg = <0x0 0x400>;

			enable-method = "psci";

			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;

			capacity-dmips-mhz = <1946>;

			dynamic-power-coefficient = <520>;

			next-level-cache = <&L2_4>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";
@@ -138,6 +148,8 @@ 
			reg = <0x0 0x500>;

			enable-method = "psci";

			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;

			capacity-dmips-mhz = <1946>;

			dynamic-power-coefficient = <520>;

			next-level-cache = <&L2_5>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";
@@ -152,6 +164,8 @@ 
			reg = <0x0 0x600>;

			enable-method = "psci";

			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;

			capacity-dmips-mhz = <1946>;

			dynamic-power-coefficient = <520>;

			next-level-cache = <&L2_6>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";
@@ -166,6 +180,8 @@ 
			reg = <0x0 0x700>;

			enable-method = "psci";

			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;

			capacity-dmips-mhz = <1985>;

			dynamic-power-coefficient = <552>;

			next-level-cache = <&L2_7>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";