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Commit 71af17fb authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Add support for A635 GPU"

parents 51edbbb2 4128054b

drivers/gpu/msm/adreno-gpulist.h

+32 −0
Original line number Diff line number Diff line
@@ -1681,6 +1681,37 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660_shima = { 
	.ctxt_record_size = 2496 * 1024,

};



static const struct adreno_a6xx_core adreno_gpu_core_a635 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A635, 6, 3, 5, ANY_ID),

		.features = ADRENO_RPMH | ADRENO_GPMU | ADRENO_APRIV |

				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_512K,

		.bus_width = 32,

		.snapshot_size = SZ_2M,

	},

	.prim_fifo_threshold = 0x00200000,

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a660_sqe.fw",

	.gmufw_name = "a660_gmu.bin",

	.zap_name = "a660_zap",

	.hwcg = a660_hwcg_regs,

	.hwcg_count = ARRAY_SIZE(a660_hwcg_regs),

	.vbif = a650_gbif_regs,

	.vbif_count = ARRAY_SIZE(a650_gbif_regs),

	.hang_detect_cycles = 0x3ffff,

	.veto_fal10 = true,

	.protected_regs = a660_protected_regs,

	.disable_tseskip = true,

	.highest_bank_bit = 15,

	.pdc_in_aop = true,

	.ctxt_record_size = 2496 * 1024,

};



static const struct adreno_gpu_core *adreno_gpulist[] = {

	&adreno_gpu_core_a306.base,

	&adreno_gpu_core_a306a.base,
@@ -1706,6 +1737,7 @@ static const struct adreno_gpu_core *adreno_gpulist[] = { 
	&adreno_gpu_core_a619.base,

	&adreno_gpu_core_a619_variant.base,

	&adreno_gpu_core_a620.base,

	&adreno_gpu_core_a635.base,

	&adreno_gpu_core_a640.base,

	&adreno_gpu_core_a650.base,

	&adreno_gpu_core_a650v2.base,

drivers/gpu/msm/adreno.h

+11 −2
Original line number Diff line number Diff line
@@ -200,6 +200,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A619 = 619,

	ADRENO_REV_A620 = 620,

	ADRENO_REV_A630 = 630,

	ADRENO_REV_A635 = 635,

	ADRENO_REV_A640 = 640,

	ADRENO_REV_A650 = 650,

	ADRENO_REV_A660 = 660,
@@ -1064,11 +1065,19 @@ ADRENO_TARGET(a618, ADRENO_REV_A618) 
ADRENO_TARGET(a619, ADRENO_REV_A619)

ADRENO_TARGET(a620, ADRENO_REV_A620)

ADRENO_TARGET(a630, ADRENO_REV_A630)

ADRENO_TARGET(a635, ADRENO_REV_A635)

ADRENO_TARGET(a640, ADRENO_REV_A640)

ADRENO_TARGET(a650, ADRENO_REV_A650)

ADRENO_TARGET(a660, ADRENO_REV_A660)

ADRENO_TARGET(a680, ADRENO_REV_A680)



/* A635 is derived from A660 and shares same logic */

static inline int adreno_is_a660(struct adreno_device *adreno_dev)

{

	unsigned int rev = ADRENO_GPUREV(adreno_dev);



	return (rev == ADRENO_REV_A660 || rev == ADRENO_REV_A635);

}



/*

 * All the derived chipsets from A615 needs to be added to this

 * list such as A616, A618, A619 etc.
@@ -1104,7 +1113,7 @@ static inline int adreno_is_a650_family(struct adreno_device *adreno_dev) 
	unsigned int rev = ADRENO_GPUREV(adreno_dev);



	return (rev == ADRENO_REV_A650 || rev == ADRENO_REV_A620 ||

		rev == ADRENO_REV_A660);

		rev == ADRENO_REV_A660 || rev == ADRENO_REV_A635);

}



static inline int adreno_is_a619_holi(struct adreno_device *adreno_dev)

drivers/gpu/msm/adreno_a6xx.c

+7 −3
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ static u32 a6xx_ifpc_pwrup_reglist[] = { 
	A6XX_CP_AHB_CNTL,

};



/* Applicable to a620, a650 and a660 */

/* Applicable to a620, a635, a650 and a660 */

static u32 a650_pwrup_reglist[] = {

	A6XX_CP_PROTECT_REG + 47,          /* Programmed for infinite span */

	A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
@@ -138,7 +138,8 @@ int a6xx_init(struct adreno_device *adreno_dev) 


	/* If the memory type is DDR 4, override the existing configuration */

	if (of_fdt_get_ddrtype() == 0x7) {

		if (adreno_is_a660_shima(adreno_dev))

		if (adreno_is_a660_shima(adreno_dev) ||

			adreno_is_a635(adreno_dev))

			adreno_dev->highest_bank_bit = 14;

		else if ((adreno_is_a650(adreno_dev) ||

				adreno_is_a660(adreno_dev)))
@@ -696,6 +697,9 @@ void a6xx_start(struct adreno_device *adreno_dev) 
	if (adreno_is_a660(adreno_dev)) {

		kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, 0x1);

		kgsl_regwrite(device, A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);



		/* Set dualQ + disable afull for A660 GPU but not for A635 */

		if (!adreno_is_a635(adreno_dev))

			kgsl_regwrite(device, A6XX_UCHE_CMDQ_CONFIG, 0x66906);

	}