Loading qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -4,6 +4,18 @@ }; &pcie0 { iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, <0x208 &apps_smmu 0x0202 0x1>, <0x210 &apps_smmu 0x0203 0x1>, <0x218 &apps_smmu 0x0204 0x1>, <0x300 &apps_smmu 0x0207 0x1>, <0x400 &apps_smmu 0x0208 0x1>, <0x500 &apps_smmu 0x020C 0x1>, <0x501 &apps_smmu 0x020E 0x1>; }; &pcie0_rp { #address-cells = <5>; #size-cells = <0>; Loading Loading
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -4,6 +4,18 @@ }; &pcie0 { iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, <0x208 &apps_smmu 0x0202 0x1>, <0x210 &apps_smmu 0x0203 0x1>, <0x218 &apps_smmu 0x0204 0x1>, <0x300 &apps_smmu 0x0207 0x1>, <0x400 &apps_smmu 0x0208 0x1>, <0x500 &apps_smmu 0x020C 0x1>, <0x501 &apps_smmu 0x020E 0x1>; }; &pcie0_rp { #address-cells = <5>; #size-cells = <0>; Loading