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Commit 7178fb0b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Ingo Molnar:
 "I'd like to apologize for this very late pull request: I was dithering
  through the week whether to send the fixes, and then yesterday Jiri's
  crash fix for a regression introduced in this cycle clearly marked
  perf/urgent as 'must merge now'.

  Most of the commits are tooling fixes, plus there's three kernel fixes
  via four commits:

    - race fix in the Intel PEBS code

    - fix an AUX bug and roll back a previous attempt

    - fix AMD family 17h generic HW cache-event perf counters

  The largest diffstat contribution comes from the AMD fix - a new event
  table is introduced, which is a fairly low risk change but has a large
  linecount"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/intel: Fix race in intel_pmu_disable_event()
  perf/x86/intel/pt: Remove software double buffering PMU capability
  perf/ring_buffer: Fix AUX software double buffering
  perf tools: Remove needless asm/unistd.h include fixing build in some places
  tools arch uapi: Copy missing unistd.h headers for arc, hexagon and riscv
  tools build: Add -ldl to the disassembler-four-args feature test
  perf cs-etm: Always allocate memory for cs_etm_queue::prev_packet
  perf cs-etm: Don't check cs_etm_queue::prev_packet validity
  perf report: Report OOM in status line in the GTK UI
  perf bench numa: Add define for RUSAGE_THREAD if not present
  tools lib traceevent: Change tag string for error
  perf annotate: Fix build on 32 bit for BPF annotation
  tools uapi x86: Sync vmx.h with the kernel
  perf bpf: Return value with unlocking in perf_env__find_btf()
  MAINTAINERS: Include vendor specific files under arch/*/events/*
  perf/x86/amd: Update generic hardware cache events for Family 17h
parents 70c9fb57 6f55967a

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -12176,6 +12176,7 @@ F: arch/*/kernel/*/*/perf_event*.c 
F:	arch/*/include/asm/perf_event.h

F:	arch/*/kernel/perf_callchain.c

F:	arch/*/events/*

F:	arch/*/events/*/*

F:	tools/perf/



PERSONALITY HANDLING

arch/x86/events/amd/core.c

+108 −3
Original line number Diff line number Diff line
@@ -116,6 +116,110 @@ static __initconst const u64 amd_hw_cache_event_ids 
 },

};



static __initconst const u64 amd_hw_cache_event_ids_f17h

				[PERF_COUNT_HW_CACHE_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]

				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {

[C(L1D)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)] = 0x0040, /* Data Cache Accesses */

		[C(RESULT_MISS)]   = 0xc860, /* L2$ access from DC Miss */

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)] = 0,

		[C(RESULT_MISS)]   = 0,

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)] = 0xff5a, /* h/w prefetch DC Fills */

		[C(RESULT_MISS)]   = 0,

	},

},

[C(L1I)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)] = 0x0080, /* Instruction cache fetches  */

		[C(RESULT_MISS)]   = 0x0081, /* Instruction cache misses   */

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)] = -1,

		[C(RESULT_MISS)]   = -1,

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)] = 0,

		[C(RESULT_MISS)]   = 0,

	},

},

[C(LL)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)] = 0,

		[C(RESULT_MISS)]   = 0,

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)] = 0,

		[C(RESULT_MISS)]   = 0,

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)] = 0,

		[C(RESULT_MISS)]   = 0,

	},

},

[C(DTLB)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)] = 0xff45, /* All L2 DTLB accesses */

		[C(RESULT_MISS)]   = 0xf045, /* L2 DTLB misses (PT walks) */

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)] = 0,

		[C(RESULT_MISS)]   = 0,

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)] = 0,

		[C(RESULT_MISS)]   = 0,

	},

},

[C(ITLB)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)] = 0x0084, /* L1 ITLB misses, L2 ITLB hits */

		[C(RESULT_MISS)]   = 0xff85, /* L1 ITLB misses, L2 misses */

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)] = -1,

		[C(RESULT_MISS)]   = -1,

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)] = -1,

		[C(RESULT_MISS)]   = -1,

	},

},

[C(BPU)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)] = 0x00c2, /* Retired Branch Instr.      */

		[C(RESULT_MISS)]   = 0x00c3, /* Retired Mispredicted BI    */

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)] = -1,

		[C(RESULT_MISS)]   = -1,

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)] = -1,

		[C(RESULT_MISS)]   = -1,

	},

},

[C(NODE)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)] = 0,

		[C(RESULT_MISS)]   = 0,

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)] = -1,

		[C(RESULT_MISS)]   = -1,

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)] = -1,

		[C(RESULT_MISS)]   = -1,

	},

},

};



/*

 * AMD Performance Monitor K7 and later, up to and including Family 16h:

 */
@@ -865,9 +969,10 @@ __init int amd_pmu_init(void) 
		x86_pmu.amd_nb_constraints = 0;

	}



	/* Events are common for all AMDs */

	memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,

	       sizeof(hw_cache_event_ids));

	if (boot_cpu_data.x86 >= 0x17)

		memcpy(hw_cache_event_ids, amd_hw_cache_event_ids_f17h, sizeof(hw_cache_event_ids));

	else

		memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, sizeof(hw_cache_event_ids));



	return 0;

}

arch/x86/events/intel/core.c

+7 −3
Original line number Diff line number Diff line
@@ -2091,15 +2091,19 @@ static void intel_pmu_disable_event(struct perf_event *event) 
	cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);

	cpuc->intel_cp_status &= ~(1ull << hwc->idx);



	if (unlikely(event->attr.precise_ip))

		intel_pmu_pebs_disable(event);



	if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {

		intel_pmu_disable_fixed(hwc);

		return;

	}



	x86_pmu_disable_event(event);



	/*

	 * Needs to be called after x86_pmu_disable_event,

	 * so we don't trigger the event without PEBS bit set.

	 */

	if (unlikely(event->attr.precise_ip))

		intel_pmu_pebs_disable(event);

}



static void intel_pmu_del_event(struct perf_event *event)

arch/x86/events/intel/pt.c

+1 −2
Original line number Diff line number Diff line
@@ -1525,8 +1525,7 @@ static __init int pt_init(void) 
	}



	if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))

		pt_pmu.pmu.capabilities =

			PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_SW_DOUBLEBUF;

		pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG;



	pt_pmu.pmu.capabilities	|= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE;

	pt_pmu.pmu.attr_groups		 = pt_attr_groups;

include/linux/perf_event.h

+0 −1
Original line number Diff line number Diff line
@@ -240,7 +240,6 @@ struct perf_event; 
#define PERF_PMU_CAP_NO_INTERRUPT		0x01

#define PERF_PMU_CAP_NO_NMI			0x02

#define PERF_PMU_CAP_AUX_NO_SG			0x04

#define PERF_PMU_CAP_AUX_SW_DOUBLEBUF		0x08

#define PERF_PMU_CAP_EXCLUSIVE			0x10

#define PERF_PMU_CAP_ITRACE			0x20

#define PERF_PMU_CAP_HETEROGENEOUS_CPUS		0x40