clk: mediatek: Add MT6779 clock support (710774e0) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/mediatek/Kconfig

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		@@ -117,6 +117,62 @@ config COMMON_CLK_MT2712_VENCSYS
		---help---
		This driver supports MediaTek MT2712 vencsys clocks.

		config COMMON_CLK_MT6779
		bool "Clock driver for MediaTek MT6779"
		depends on (ARCH_MEDIATEK && ARM64) \|\| COMPILE_TEST
		select COMMON_CLK_MEDIATEK
		default ARCH_MEDIATEK && ARM64
		help
		This driver supports MediaTek MT6779 basic clocks.

		config COMMON_CLK_MT6779_MMSYS
		bool "Clock driver for MediaTek MT6779 mmsys"
		depends on COMMON_CLK_MT6779
		help
		This driver supports MediaTek MT6779 mmsys clocks.

		config COMMON_CLK_MT6779_IMGSYS
		bool "Clock driver for MediaTek MT6779 imgsys"
		depends on COMMON_CLK_MT6779
		help
		This driver supports MediaTek MT6779 imgsys clocks.

		config COMMON_CLK_MT6779_IPESYS
		bool "Clock driver for MediaTek MT6779 ipesys"
		depends on COMMON_CLK_MT6779
		help
		This driver supports MediaTek MT6779 ipesys clocks.

		config COMMON_CLK_MT6779_CAMSYS
		bool "Clock driver for MediaTek MT6779 camsys"
		depends on COMMON_CLK_MT6779
		help
		This driver supports MediaTek MT6779 camsys clocks.

		config COMMON_CLK_MT6779_VDECSYS
		bool "Clock driver for MediaTek MT6779 vdecsys"
		depends on COMMON_CLK_MT6779
		help
		This driver supports MediaTek MT6779 vdecsys clocks.

		config COMMON_CLK_MT6779_VENCSYS
		bool "Clock driver for MediaTek MT6779 vencsys"
		depends on COMMON_CLK_MT6779
		help
		This driver supports MediaTek MT6779 vencsys clocks.

		config COMMON_CLK_MT6779_MFGCFG
		bool "Clock driver for MediaTek MT6779 mfgcfg"
		depends on COMMON_CLK_MT6779
		help
		This driver supports MediaTek MT6779 mfgcfg clocks.

		config COMMON_CLK_MT6779_AUDSYS
		bool "Clock driver for Mediatek MT6779 audsys"
		depends on COMMON_CLK_MT6779
		help
		This driver supports Mediatek MT6779 audsys clocks.

		config COMMON_CLK_MT6797
		bool "Clock driver for MediaTek MT6797"
		depends on (ARCH_MEDIATEK && ARM64) \|\| COMPILE_TEST

drivers/clk/mediatek/Makefile

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		# SPDX-License-Identifier: GPL-2.0
		obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o

		obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
		obj-$(CONFIG_COMMON_CLK_MT6779_MMSYS) += clk-mt6779-mm.o
		obj-$(CONFIG_COMMON_CLK_MT6779_IMGSYS) += clk-mt6779-img.o
		obj-$(CONFIG_COMMON_CLK_MT6779_IPESYS) += clk-mt6779-ipe.o
		obj-$(CONFIG_COMMON_CLK_MT6779_CAMSYS) += clk-mt6779-cam.o
		obj-$(CONFIG_COMMON_CLK_MT6779_VDECSYS) += clk-mt6779-vdec.o
		obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o
		obj-$(CONFIG_COMMON_CLK_MT6779_MFGCFG) += clk-mt6779-mfg.o
		obj-$(CONFIG_COMMON_CLK_MT6779_AUDSYS) += clk-mt6779-aud.o
		obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
		obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
		obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o

drivers/clk/mediatek/clk-mt6779-aud.c

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		// SPDX-License-Identifier: GPL-2.0
		/*
		* Copyright (c) 2019 MediaTek Inc.
		* Author: Wendell Lin <wendell.lin@mediatek.com>
		*/

		#include <linux/clk-provider.h>
		#include <linux/of.h>
		#include <linux/of_address.h>
		#include <linux/of_device.h>
		#include <linux/platform_device.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		#include <dt-bindings/clock/mt6779-clk.h>

		static const struct mtk_gate_regs audio0_cg_regs = {
		.set_ofs = 0x0,
		.clr_ofs = 0x0,
		.sta_ofs = 0x0,
		};

		static const struct mtk_gate_regs audio1_cg_regs = {
		.set_ofs = 0x4,
		.clr_ofs = 0x4,
		.sta_ofs = 0x4,
		};

		#define GATE_AUDIO0(_id, _name, _parent, _shift) \
		GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
		&mtk_clk_gate_ops_no_setclr)
		#define GATE_AUDIO1(_id, _name, _parent, _shift) \
		GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
		&mtk_clk_gate_ops_no_setclr)

		static const struct mtk_gate audio_clks[] = {
		/* AUDIO0 */
		GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
		GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
		GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
		GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
		"aud_eng2_sel", 18),
		GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
		"aud_eng1_sel", 19),
		GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
		GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
		GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
		GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
		"audio_sel", 26),
		GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
		GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
		/* AUDIO1 */
		GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
		"audio_sel", 4),
		GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
		"audio_sel", 5),
		GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
		"audio_sel", 6),
		GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
		"audio_sel", 7),
		GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
		"audio_sel", 8),
		GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
		"audio_sel", 12),
		GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
		"audio_sel", 13),
		GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
		"audio_sel", 14),
		GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
		"audio_h_sel", 15),
		GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
		"audio_h_sel", 16),
		GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
		"audio_h_sel", 17),
		GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
		"audio_sel", 20),
		GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
		"audio_h_sel",
		21),
		GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
		28),
		GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
		"audio_sel", 29),
		GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
		"audio_sel", 30),
		GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
		"audio_h_sel", 31),
		};

		static const struct of_device_id of_match_clk_mt6779_aud[] = {
		{ .compatible = "mediatek,mt6779-audio", },
		{}
		};

		static int clk_mt6779_aud_probe(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		struct device_node *node = pdev->dev.of_node;

		clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);

		mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
		clk_data);

		return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
		}

		static struct platform_driver clk_mt6779_aud_drv = {
		.probe = clk_mt6779_aud_probe,
		.driver = {
		.name = "clk-mt6779-aud",
		.of_match_table = of_match_clk_mt6779_aud,
		},
		};

		builtin_platform_driver(clk_mt6779_aud_drv);

drivers/clk/mediatek/clk-mt6779-cam.c

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		// SPDX-License-Identifier: GPL-2.0
		/*
		* Copyright (c) 2019 MediaTek Inc.
		* Author: Wendell Lin <wendell.lin@mediatek.com>
		*/

		#include <linux/clk-provider.h>
		#include <linux/platform_device.h>
		#include <dt-bindings/clock/mt6779-clk.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		static const struct mtk_gate_regs cam_cg_regs = {
		.set_ofs = 0x0004,
		.clr_ofs = 0x0008,
		.sta_ofs = 0x0000,
		};

		#define GATE_CAM(_id, _name, _parent, _shift) \
		GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
		&mtk_clk_gate_ops_setclr)

		static const struct mtk_gate cam_clks[] = {
		GATE_CAM(CLK_CAM_LARB10, "camsys_larb10", "cam_sel", 0),
		GATE_CAM(CLK_CAM_DFP_VAD, "camsys_dfp_vad", "cam_sel", 1),
		GATE_CAM(CLK_CAM_LARB11, "camsys_larb11", "cam_sel", 2),
		GATE_CAM(CLK_CAM_LARB9, "camsys_larb9", "cam_sel", 3),
		GATE_CAM(CLK_CAM_CAM, "camsys_cam", "cam_sel", 6),
		GATE_CAM(CLK_CAM_CAMTG, "camsys_camtg", "cam_sel", 7),
		GATE_CAM(CLK_CAM_SENINF, "camsys_seninf", "cam_sel", 8),
		GATE_CAM(CLK_CAM_CAMSV0, "camsys_camsv0", "cam_sel", 9),
		GATE_CAM(CLK_CAM_CAMSV1, "camsys_camsv1", "cam_sel", 10),
		GATE_CAM(CLK_CAM_CAMSV2, "camsys_camsv2", "cam_sel", 11),
		GATE_CAM(CLK_CAM_CAMSV3, "camsys_camsv3", "cam_sel", 12),
		GATE_CAM(CLK_CAM_CCU, "camsys_ccu", "cam_sel", 13),
		GATE_CAM(CLK_CAM_FAKE_ENG, "camsys_fake_eng", "cam_sel", 14),
		};

		static const struct of_device_id of_match_clk_mt6779_cam[] = {
		{ .compatible = "mediatek,mt6779-camsys", },
		{}
		};

		static int clk_mt6779_cam_probe(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		struct device_node *node = pdev->dev.of_node;

		clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);

		mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
		clk_data);

		return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
		}

		static struct platform_driver clk_mt6779_cam_drv = {
		.probe = clk_mt6779_cam_probe,
		.driver = {
		.name = "clk-mt6779-cam",
		.of_match_table = of_match_clk_mt6779_cam,
		},
		};

		builtin_platform_driver(clk_mt6779_cam_drv);

drivers/clk/mediatek/clk-mt6779-img.c

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		// SPDX-License-Identifier: GPL-2.0
		/*
		* Copyright (c) 2019 MediaTek Inc.
		* Author: Wendell Lin <wendell.lin@mediatek.com>
		*/

		#include <linux/clk-provider.h>
		#include <linux/platform_device.h>
		#include <dt-bindings/clock/mt6779-clk.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		static const struct mtk_gate_regs img_cg_regs = {
		.set_ofs = 0x0004,
		.clr_ofs = 0x0008,
		.sta_ofs = 0x0000,
		};

		#define GATE_IMG(_id, _name, _parent, _shift) \
		GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
		&mtk_clk_gate_ops_setclr)

		static const struct mtk_gate img_clks[] = {
		GATE_IMG(CLK_IMG_LARB5, "imgsys_larb5", "img_sel", 0),
		GATE_IMG(CLK_IMG_LARB6, "imgsys_larb6", "img_sel", 1),
		GATE_IMG(CLK_IMG_DIP, "imgsys_dip", "img_sel", 2),
		GATE_IMG(CLK_IMG_MFB, "imgsys_mfb", "img_sel", 6),
		GATE_IMG(CLK_IMG_WPE_A, "imgsys_wpe_a", "img_sel", 7),
		};

		static const struct of_device_id of_match_clk_mt6779_img[] = {
		{ .compatible = "mediatek,mt6779-imgsys", },
		{}
		};

		static int clk_mt6779_img_probe(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		struct device_node *node = pdev->dev.of_node;

		clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);

		mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
		clk_data);

		return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
		}

		static struct platform_driver clk_mt6779_img_drv = {
		.probe = clk_mt6779_img_probe,
		.driver = {
		.name = "clk-mt6779-img",
		.of_match_table = of_match_clk_mt6779_img,
		},
		};

		builtin_platform_driver(clk_mt6779_img_drv);