Loading qcom/holi.dtsi +6 −2 Original line number Diff line number Diff line Loading @@ -2159,8 +2159,12 @@ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "core", "iface", "ice_core"; qcom,ice-clk-rates = <300000000 100000000>; interconnects = <&system_noc MASTER_EMMC &bimc SLAVE_EBI>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_EMMC_CFG>; Loading Loading
qcom/holi.dtsi +6 −2 Original line number Diff line number Diff line Loading @@ -2159,8 +2159,12 @@ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "core", "iface", "ice_core"; qcom,ice-clk-rates = <300000000 100000000>; interconnects = <&system_noc MASTER_EMMC &bimc SLAVE_EBI>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_EMMC_CFG>; Loading