Loading msm/dsi/dsi_catalog.c +0 −4 Original line number Diff line number Diff line Loading @@ -77,7 +77,6 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, ctrl->ops.reg_dump_to_buffer = dsi_ctrl_hw_14_reg_dump_to_buffer; ctrl->ops.schedule_dma_cmd = NULL; ctrl->ops.get_cont_splash_status = NULL; ctrl->ops.kickoff_command_non_embedded_mode = NULL; ctrl->ops.config_clk_gating = NULL; break; Loading @@ -93,7 +92,6 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, ctrl->ops.clamp_enable = NULL; ctrl->ops.clamp_disable = NULL; ctrl->ops.schedule_dma_cmd = NULL; ctrl->ops.get_cont_splash_status = NULL; ctrl->ops.kickoff_command_non_embedded_mode = NULL; ctrl->ops.config_clk_gating = NULL; break; Loading @@ -102,8 +100,6 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, case DSI_CTRL_VERSION_2_4: ctrl->ops.phy_reset_config = dsi_ctrl_hw_22_phy_reset_config; ctrl->ops.config_clk_gating = dsi_ctrl_hw_22_config_clk_gating; ctrl->ops.get_cont_splash_status = dsi_ctrl_hw_22_get_cont_splash_status; ctrl->ops.setup_lane_map = dsi_ctrl_hw_20_setup_lane_map; ctrl->ops.wait_for_lane_idle = dsi_ctrl_hw_20_wait_for_lane_idle; Loading msm/dsi/dsi_catalog.h +0 −1 Original line number Diff line number Diff line Loading @@ -233,7 +233,6 @@ void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl, u32 flags); /* Definitions specific to 2.2 DSI controller hardware */ bool dsi_ctrl_hw_22_get_cont_splash_status(struct dsi_ctrl_hw *ctrl); void dsi_ctrl_hw_22_config_clk_gating(struct dsi_ctrl_hw *ctrl, bool enable, enum dsi_clk_gate_type clk_selection); Loading msm/dsi/dsi_ctrl_hw.h +0 −6 Original line number Diff line number Diff line Loading @@ -572,12 +572,6 @@ struct dsi_ctrl_hw_ops { u32 pkt_size, u32 *hw_read_cnt); /** * get_cont_splash_status() - get continuous splash status * @ctrl: Pointer to the controller host hardware. */ bool (*get_cont_splash_status)(struct dsi_ctrl_hw *ctrl); /** * wait_for_lane_idle() - wait for DSI lanes to go to idle state * @ctrl: Pointer to the controller host hardware. Loading msm/dsi/dsi_ctrl_hw_2_2.c +0 −19 Original line number Diff line number Diff line Loading @@ -51,25 +51,6 @@ void dsi_ctrl_hw_22_schedule_dma_cmd(struct dsi_ctrl_hw *ctrl, int line_no) DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL, reg); } /* * dsi_ctrl_hw_22_get_cont_splash_status() - to verify whether continuous * splash is enabled or not * @ctrl: Pointer to the controller host hardware. * * Return: Return Continuous splash status */ bool dsi_ctrl_hw_22_get_cont_splash_status(struct dsi_ctrl_hw *ctrl) { u32 reg = 0; /** * DSI scratch register 1 is used to notify whether continuous * splash is enabled or not by bootloader */ reg = DSI_R32(ctrl, DSI_SCRATCH_REGISTER_1); return reg == 0x1; } /* * dsi_ctrl_hw_kickoff_non_embedded_mode()-Kickoff cmd in non-embedded mode * @ctrl: - Pointer to the controller host hardware. Loading msm/dsi/dsi_display.c +1 −35 Original line number Diff line number Diff line Loading @@ -1029,32 +1029,6 @@ static void _dsi_display_setup_misr(struct dsi_display *display) } } /** * dsi_display_get_cont_splash_status - Get continuous splash status. * @dsi_display: DSI display handle. * * Return: boolean to signify whether continuous splash is enabled. */ static bool dsi_display_get_cont_splash_status(struct dsi_display *display) { u32 val = 0; int i; struct dsi_display_ctrl *ctrl; struct dsi_ctrl_hw *hw; display_for_each_ctrl(i, display) { ctrl = &(display->ctrl[i]); if (!ctrl || !ctrl->ctrl) continue; hw = &(ctrl->ctrl->hw); val = hw->ops.get_cont_splash_status(hw); if (!val) return false; } return true; } int dsi_display_set_power(struct drm_connector *connector, int power_mode, void *disp) { Loading Loading @@ -4155,13 +4129,7 @@ int dsi_display_cont_splash_config(void *dsi_display) mutex_lock(&display->display_lock); /* Verify whether continuous splash is enabled or not */ display->is_cont_splash_enabled = dsi_display_get_cont_splash_status(display); if (!display->is_cont_splash_enabled) { pr_err("Continuous splash is not enabled\n"); goto splash_disabled; } display->is_cont_splash_enabled = true; /* Update splash status for clock manager */ dsi_display_clk_mngr_update_splash_status(display->clk_mngr, Loading Loading @@ -4206,8 +4174,6 @@ int dsi_display_cont_splash_config(void *dsi_display) /* Update splash status for clock manager */ dsi_display_clk_mngr_update_splash_status(display->clk_mngr, false); splash_disabled: pm_runtime_put_sync(display->drm_dev->dev); display->is_cont_splash_enabled = false; mutex_unlock(&display->display_lock); Loading Loading
msm/dsi/dsi_catalog.c +0 −4 Original line number Diff line number Diff line Loading @@ -77,7 +77,6 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, ctrl->ops.reg_dump_to_buffer = dsi_ctrl_hw_14_reg_dump_to_buffer; ctrl->ops.schedule_dma_cmd = NULL; ctrl->ops.get_cont_splash_status = NULL; ctrl->ops.kickoff_command_non_embedded_mode = NULL; ctrl->ops.config_clk_gating = NULL; break; Loading @@ -93,7 +92,6 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, ctrl->ops.clamp_enable = NULL; ctrl->ops.clamp_disable = NULL; ctrl->ops.schedule_dma_cmd = NULL; ctrl->ops.get_cont_splash_status = NULL; ctrl->ops.kickoff_command_non_embedded_mode = NULL; ctrl->ops.config_clk_gating = NULL; break; Loading @@ -102,8 +100,6 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, case DSI_CTRL_VERSION_2_4: ctrl->ops.phy_reset_config = dsi_ctrl_hw_22_phy_reset_config; ctrl->ops.config_clk_gating = dsi_ctrl_hw_22_config_clk_gating; ctrl->ops.get_cont_splash_status = dsi_ctrl_hw_22_get_cont_splash_status; ctrl->ops.setup_lane_map = dsi_ctrl_hw_20_setup_lane_map; ctrl->ops.wait_for_lane_idle = dsi_ctrl_hw_20_wait_for_lane_idle; Loading
msm/dsi/dsi_catalog.h +0 −1 Original line number Diff line number Diff line Loading @@ -233,7 +233,6 @@ void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl, u32 flags); /* Definitions specific to 2.2 DSI controller hardware */ bool dsi_ctrl_hw_22_get_cont_splash_status(struct dsi_ctrl_hw *ctrl); void dsi_ctrl_hw_22_config_clk_gating(struct dsi_ctrl_hw *ctrl, bool enable, enum dsi_clk_gate_type clk_selection); Loading
msm/dsi/dsi_ctrl_hw.h +0 −6 Original line number Diff line number Diff line Loading @@ -572,12 +572,6 @@ struct dsi_ctrl_hw_ops { u32 pkt_size, u32 *hw_read_cnt); /** * get_cont_splash_status() - get continuous splash status * @ctrl: Pointer to the controller host hardware. */ bool (*get_cont_splash_status)(struct dsi_ctrl_hw *ctrl); /** * wait_for_lane_idle() - wait for DSI lanes to go to idle state * @ctrl: Pointer to the controller host hardware. Loading
msm/dsi/dsi_ctrl_hw_2_2.c +0 −19 Original line number Diff line number Diff line Loading @@ -51,25 +51,6 @@ void dsi_ctrl_hw_22_schedule_dma_cmd(struct dsi_ctrl_hw *ctrl, int line_no) DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL, reg); } /* * dsi_ctrl_hw_22_get_cont_splash_status() - to verify whether continuous * splash is enabled or not * @ctrl: Pointer to the controller host hardware. * * Return: Return Continuous splash status */ bool dsi_ctrl_hw_22_get_cont_splash_status(struct dsi_ctrl_hw *ctrl) { u32 reg = 0; /** * DSI scratch register 1 is used to notify whether continuous * splash is enabled or not by bootloader */ reg = DSI_R32(ctrl, DSI_SCRATCH_REGISTER_1); return reg == 0x1; } /* * dsi_ctrl_hw_kickoff_non_embedded_mode()-Kickoff cmd in non-embedded mode * @ctrl: - Pointer to the controller host hardware. Loading
msm/dsi/dsi_display.c +1 −35 Original line number Diff line number Diff line Loading @@ -1029,32 +1029,6 @@ static void _dsi_display_setup_misr(struct dsi_display *display) } } /** * dsi_display_get_cont_splash_status - Get continuous splash status. * @dsi_display: DSI display handle. * * Return: boolean to signify whether continuous splash is enabled. */ static bool dsi_display_get_cont_splash_status(struct dsi_display *display) { u32 val = 0; int i; struct dsi_display_ctrl *ctrl; struct dsi_ctrl_hw *hw; display_for_each_ctrl(i, display) { ctrl = &(display->ctrl[i]); if (!ctrl || !ctrl->ctrl) continue; hw = &(ctrl->ctrl->hw); val = hw->ops.get_cont_splash_status(hw); if (!val) return false; } return true; } int dsi_display_set_power(struct drm_connector *connector, int power_mode, void *disp) { Loading Loading @@ -4155,13 +4129,7 @@ int dsi_display_cont_splash_config(void *dsi_display) mutex_lock(&display->display_lock); /* Verify whether continuous splash is enabled or not */ display->is_cont_splash_enabled = dsi_display_get_cont_splash_status(display); if (!display->is_cont_splash_enabled) { pr_err("Continuous splash is not enabled\n"); goto splash_disabled; } display->is_cont_splash_enabled = true; /* Update splash status for clock manager */ dsi_display_clk_mngr_update_splash_status(display->clk_mngr, Loading Loading @@ -4206,8 +4174,6 @@ int dsi_display_cont_splash_config(void *dsi_display) /* Update splash status for clock manager */ dsi_display_clk_mngr_update_splash_status(display->clk_mngr, false); splash_disabled: pm_runtime_put_sync(display->drm_dev->dev); display->is_cont_splash_enabled = false; mutex_unlock(&display->display_lock); Loading