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Commit 706967db authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "serial: msm_geni_serial: Double clock-divider for kona based hw"

parents 2b7be994 930f31f0

drivers/platform/msm/msm-geni-se.c

+0 −3
Original line number Diff line number Diff line
@@ -110,9 +110,6 @@ struct geni_se_device { 
	bool vote_for_bw;

};



/* Offset of QUPV3 Hardware Version Register */

#define QUPV3_HW_VER (0x4)



#define HW_VER_MAJOR_MASK GENMASK(31, 28)

#define HW_VER_MAJOR_SHFT 28

#define HW_VER_MINOR_MASK GENMASK(27, 16)

drivers/tty/serial/msm_geni_serial.c

+10 −14
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ 


#define DMA_RX_BUF_SIZE		(2048)

#define UART_CONSOLE_RX_WM	(2)

#define QUP_VER			(0x20050000)

struct msm_geni_serial_port {

	struct uart_port uport;

	char name[20];
@@ -189,6 +190,11 @@ static atomic_t uart_line_id = ATOMIC_INIT(0); 
static struct msm_geni_serial_port msm_geni_console_port;

static struct msm_geni_serial_port msm_geni_serial_ports[GENI_UART_NR_PORTS];



static int hw_version_info(void __iomem *base_addr)

{

	return geni_read_reg(base_addr, QUPV3_HW_VER);

}



static void msm_geni_serial_config_port(struct uart_port *uport, int cfg_flags)

{

	if (cfg_flags & UART_CONFIG_TYPE)
@@ -1825,10 +1831,6 @@ static void msm_geni_serial_set_termios(struct uart_port *uport, 
	unsigned long clk_rate;

	unsigned long flags;



	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	if (!uart_console(uport)) {

		int ret = msm_geni_serial_power_on(uport);
@@ -1853,6 +1855,8 @@ static void msm_geni_serial_set_termios(struct uart_port *uport, 
	if (clk_div <= 0)

		goto exit_set_termios;



	if (hw_version_info(uport->membase) >= QUP_VER)

		clk_div *= 2;

	uport->uartclk = clk_rate;

	clk_set_rate(port->serial_rsc.se_clk, clk_rate);

	ser_clk_cfg |= SER_CLK_EN;
@@ -2129,6 +2133,8 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, 
		goto exit_geni_serial_earlyconsetup;

	}



	if (hw_version_info(uport->membase) >= QUP_VER)

		clk_div *= 2;

	s_clk_cfg |= SER_CLK_EN;

	s_clk_cfg |= (clk_div << CLK_DIV_SHFT);
@@ -2139,10 +2145,6 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, 
	msm_geni_serial_poll_cancel_tx(uport);

	msm_geni_serial_abort_rx(uport);



	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	se_get_packing_config(8, 1, false, &cfg0, &cfg1);

	geni_se_init(uport->membase, (DEF_FIFO_DEPTH_WORDS >> 1),

					(DEF_FIFO_DEPTH_WORDS - 2));
@@ -2536,12 +2538,6 @@ static int msm_geni_serial_probe(struct platform_device *pdev) 
		pm_runtime_enable(&pdev->dev);

	}



	se_geni_clks_on(&dev_port->serial_rsc);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);

	se_geni_clks_off(&dev_port->serial_rsc);



	dev_info(&pdev->dev, "Serial port%d added.FifoSize %d is_console%d\n",

				line, uport->fifosize, is_console);

	device_create_file(uport->dev, &dev_attr_loopback);

include/linux/msm-geni-se.h

+2 −0
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ struct se_geni_rsc { 
	int	clk_freq_out;

};



/* Offset of QUPV3 Hardware Version Register */

#define QUPV3_HW_VER (0x4)

#define PINCTRL_DEFAULT	"default"

#define PINCTRL_SLEEP	"sleep"