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Commit 7066fdd0 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Stephen Boyd
Browse files

clk: qcom: clk-smd-rpm: add msm8996 rpmclks 



Add all RPM controlled clocks on msm8996 platform

[srini: Fixed various issues with offsets and made names specific to msm8996]
Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent d4a69583

Documentation/devicetree/bindings/clock/qcom,rpmcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Required properties : 
			"qcom,rpmcc-msm8916", "qcom,rpmcc"

			"qcom,rpmcc-msm8974", "qcom,rpmcc"

			"qcom,rpmcc-apq8064", "qcom,rpmcc"

			"qcom,rpmcc-msm8996", "qcom,rpmcc"



- #clock-cells : shall contain 1

drivers/clk/qcom/clk-smd-rpm.c

+82 −0
Original line number Diff line number Diff line
@@ -530,9 +530,91 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { 
	.clks = msm8974_clks,

	.num_clks = ARRAY_SIZE(msm8974_clks),

};



/* msm8996 */

DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);

DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);

DEFINE_CLK_SMD_RPM(msm8996, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);

DEFINE_CLK_SMD_RPM(msm8996, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);

DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,

		   QCOM_SMD_RPM_MMAXI_CLK, 0);

DEFINE_CLK_SMD_RPM(msm8996, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);

DEFINE_CLK_SMD_RPM(msm8996, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);

DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,

			  QCOM_SMD_RPM_AGGR_CLK, 1, 1000);

DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,

			  QCOM_SMD_RPM_AGGR_CLK, 2, 1000);

DEFINE_CLK_SMD_RPM_QDSS(msm8996, qdss_clk, qdss_a_clk,

			QCOM_SMD_RPM_MISC_CLK, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_a, 0xb);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_a, 0xc);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_a, 0xd);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5);



static struct clk_smd_rpm *msm8996_clks[] = {

	[RPM_SMD_PCNOC_CLK] = &msm8996_pcnoc_clk,

	[RPM_SMD_PCNOC_A_CLK] = &msm8996_pcnoc_a_clk,

	[RPM_SMD_SNOC_CLK] = &msm8996_snoc_clk,

	[RPM_SMD_SNOC_A_CLK] = &msm8996_snoc_a_clk,

	[RPM_SMD_CNOC_CLK] = &msm8996_cnoc_clk,

	[RPM_SMD_CNOC_A_CLK] = &msm8996_cnoc_a_clk,

	[RPM_SMD_BIMC_CLK] = &msm8996_bimc_clk,

	[RPM_SMD_BIMC_A_CLK] = &msm8996_bimc_a_clk,

	[RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,

	[RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,

	[RPM_SMD_IPA_CLK] = &msm8996_ipa_clk,

	[RPM_SMD_IPA_A_CLK] = &msm8996_ipa_a_clk,

	[RPM_SMD_CE1_CLK] = &msm8996_ce1_clk,

	[RPM_SMD_CE1_A_CLK] = &msm8996_ce1_a_clk,

	[RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,

	[RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,

	[RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,

	[RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,

	[RPM_SMD_QDSS_CLK] = &msm8996_qdss_clk,

	[RPM_SMD_QDSS_A_CLK] = &msm8996_qdss_a_clk,

	[RPM_SMD_BB_CLK1] = &msm8996_bb_clk1,

	[RPM_SMD_BB_CLK1_A] = &msm8996_bb_clk1_a,

	[RPM_SMD_BB_CLK2] = &msm8996_bb_clk2,

	[RPM_SMD_BB_CLK2_A] = &msm8996_bb_clk2_a,

	[RPM_SMD_RF_CLK1] = &msm8996_rf_clk1,

	[RPM_SMD_RF_CLK1_A] = &msm8996_rf_clk1_a,

	[RPM_SMD_RF_CLK2] = &msm8996_rf_clk2,

	[RPM_SMD_RF_CLK2_A] = &msm8996_rf_clk2_a,

	[RPM_SMD_LN_BB_CLK] = &msm8996_ln_bb_clk,

	[RPM_SMD_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk,

	[RPM_SMD_DIV_CLK1] = &msm8996_div_clk1,

	[RPM_SMD_DIV_A_CLK1] = &msm8996_div_clk1_a,

	[RPM_SMD_DIV_CLK2] = &msm8996_div_clk2,

	[RPM_SMD_DIV_A_CLK2] = &msm8996_div_clk2_a,

	[RPM_SMD_DIV_CLK3] = &msm8996_div_clk3,

	[RPM_SMD_DIV_A_CLK3] = &msm8996_div_clk3_a,

	[RPM_SMD_BB_CLK1_PIN] = &msm8996_bb_clk1_pin,

	[RPM_SMD_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin,

	[RPM_SMD_BB_CLK2_PIN] = &msm8996_bb_clk2_pin,

	[RPM_SMD_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin,

	[RPM_SMD_RF_CLK1_PIN] = &msm8996_rf_clk1_pin,

	[RPM_SMD_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin,

	[RPM_SMD_RF_CLK2_PIN] = &msm8996_rf_clk2_pin,

	[RPM_SMD_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin,

};



static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {

	.clks = msm8996_clks,

	.num_clks = ARRAY_SIZE(msm8996_clks),

};



static const struct of_device_id rpm_smd_clk_match_table[] = {

	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },

	{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },

	{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },

	{ }

};

MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);

include/dt-bindings/clock/qcom,rpmcc.h

+14 −0
Original line number Diff line number Diff line
@@ -104,5 +104,19 @@ 
#define RPM_SMD_CXO_A1_A_PIN			59

#define RPM_SMD_CXO_A2_PIN			60

#define RPM_SMD_CXO_A2_A_PIN			61

#define RPM_SMD_AGGR1_NOC_CLK			62

#define RPM_SMD_AGGR1_NOC_A_CLK			63

#define RPM_SMD_AGGR2_NOC_CLK			64

#define RPM_SMD_AGGR2_NOC_A_CLK			65

#define RPM_SMD_MMAXI_CLK			66

#define RPM_SMD_MMAXI_A_CLK			67

#define RPM_SMD_IPA_CLK				68

#define RPM_SMD_IPA_A_CLK			69

#define RPM_SMD_CE1_CLK				70

#define RPM_SMD_CE1_A_CLK			71

#define RPM_SMD_DIV_CLK3			72

#define RPM_SMD_DIV_A_CLK3			73

#define RPM_SMD_LN_BB_CLK			74

#define RPM_SMD_LN_BB_A_CLK			75



#endif

include/linux/soc/qcom/smd-rpm.h

+4 −0
Original line number Diff line number Diff line
@@ -26,6 +26,10 @@ struct qcom_smd_rpm; 
#define QCOM_SMD_RPM_SMPB	0x62706d73

#define QCOM_SMD_RPM_SPDM	0x63707362

#define QCOM_SMD_RPM_VSA	0x00617376

#define QCOM_SMD_RPM_MMAXI_CLK	0x69786d6d

#define QCOM_SMD_RPM_IPA_CLK	0x617069

#define QCOM_SMD_RPM_CE_CLK	0x6563

#define QCOM_SMD_RPM_AGGR_CLK	0x72676761



int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,

		       int state,