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Commit 70457520 authored by Brett Creeley's avatar Brett Creeley Committed by Jeff Kirsher
Browse files

ice: configure GLINT_ITR to always have an ITR gran of 2 



Instead of hoping that our ITR granularity will be 2 usec program the
GLINT_CTL register to make sure the ITR granularity is always 2 usecs.

Now that we know what the ITR granularity will be get rid of the check
in ice_probe() to verify our previous assumption.

Signed-off-by: default avatarBrett Creeley <brett.creeley@intel.com>
Signed-off-by: default avatarAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 80ed404a

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

+10 −0
Original line number Diff line number Diff line
@@ -106,6 +106,16 @@ 
#define VPGEN_VFRTRIG_VFSWR_M			BIT(0)

#define PFHMC_ERRORDATA				0x00520500

#define PFHMC_ERRORINFO				0x00520400

#define GLINT_CTL				0x0016CC54

#define GLINT_CTL_DIS_AUTOMASK_M		BIT(0)

#define GLINT_CTL_ITR_GRAN_200_S		16

#define GLINT_CTL_ITR_GRAN_200_M		ICE_M(0xF, 16)

#define GLINT_CTL_ITR_GRAN_100_S		20

#define GLINT_CTL_ITR_GRAN_100_M		ICE_M(0xF, 20)

#define GLINT_CTL_ITR_GRAN_50_S			24

#define GLINT_CTL_ITR_GRAN_50_M			ICE_M(0xF, 24)

#define GLINT_CTL_ITR_GRAN_25_S			28

#define GLINT_CTL_ITR_GRAN_25_M			ICE_M(0xF, 28)

#define GLINT_DYN_CTL(_INT)			(0x00160000 + ((_INT) * 4))

#define GLINT_DYN_CTL_INTENA_M			BIT(0)

#define GLINT_DYN_CTL_CLEARPBA_M		BIT(1)

drivers/net/ethernet/intel/ice/ice_lib.c

+33 −0
Original line number Diff line number Diff line
@@ -1713,6 +1713,37 @@ static u32 ice_intrl_usec_to_reg(u8 intrl, u8 gran) 
	return 0;

}



/**

 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set

 * @hw: board specific structure

 */

static void ice_cfg_itr_gran(struct ice_hw *hw)

{

	u32 regval = rd32(hw, GLINT_CTL);



	/* no need to update global register if ITR gran is already set */

	if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) &&

	    (((regval & GLINT_CTL_ITR_GRAN_200_M) >>

	     GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) &&

	    (((regval & GLINT_CTL_ITR_GRAN_100_M) >>

	     GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) &&

	    (((regval & GLINT_CTL_ITR_GRAN_50_M) >>

	     GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) &&

	    (((regval & GLINT_CTL_ITR_GRAN_25_M) >>

	      GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US))

		return;



	regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) &

		  GLINT_CTL_ITR_GRAN_200_M) |

		 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) &

		  GLINT_CTL_ITR_GRAN_100_M) |

		 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) &

		  GLINT_CTL_ITR_GRAN_50_M) |

		 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) &

		  GLINT_CTL_ITR_GRAN_25_M);

	wr32(hw, GLINT_CTL, regval);

}



/**

 * ice_cfg_itr - configure the initial interrupt throttle values

 * @hw: pointer to the HW structure
@@ -1725,6 +1756,8 @@ static u32 ice_intrl_usec_to_reg(u8 intrl, u8 gran) 
static void

ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector, u16 vector)

{

	ice_cfg_itr_gran(hw);



	if (q_vector->num_ring_rx) {

		struct ice_ring_container *rc = &q_vector->rx;

drivers/net/ethernet/intel/ice/ice_main.c

+0 −18
Original line number Diff line number Diff line
@@ -2032,23 +2032,6 @@ static int ice_init_interrupt_scheme(struct ice_pf *pf) 
	return 0;

}



/**

 * ice_verify_itr_gran - verify driver's assumption of ITR granularity

 * @pf: pointer to the PF structure

 *

 * There is no error returned here because the driver will be able to handle a

 * different ITR granularity, but interrupt moderation will not be accurate if

 * the driver's assumptions are not verified. This assumption is made so we can

 * use constants in the hot path instead of accessing structure members.

 */

static void ice_verify_itr_gran(struct ice_pf *pf)

{

	if (pf->hw.itr_gran != (ICE_ITR_GRAN_S << 1))

		dev_warn(&pf->pdev->dev,

			 "%d ITR granularity assumption is invalid, actual ITR granularity is %d. Interrupt moderation will be inaccurate!\n",

			 (ICE_ITR_GRAN_S << 1), pf->hw.itr_gran);

}



/**

 * ice_verify_cacheline_size - verify driver's assumption of 64 Byte cache lines

 * @pf: pointer to the PF structure
@@ -2212,7 +2195,6 @@ static int ice_probe(struct pci_dev *pdev, 
	mod_timer(&pf->serv_tmr, round_jiffies(jiffies + pf->serv_tmr_period));



	ice_verify_cacheline_size(pf);

	ice_verify_itr_gran(pf);



	return 0;

drivers/net/ethernet/intel/ice/ice_txrx.h

+1 −0
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@ enum ice_rx_dtype { 
#define ITR_IS_DYNAMIC(setting) (!!((setting) & ICE_ITR_DYNAMIC))

#define ITR_TO_REG(setting)	((setting) & ~ICE_ITR_DYNAMIC)

#define ICE_ITR_GRAN_S		1	/* Assume ITR granularity is 2us */

#define ICE_ITR_GRAN_US		BIT(ICE_ITR_GRAN_S)

#define ICE_ITR_MASK		0x1FFE	/* ITR register value alignment mask */

#define ITR_REG_ALIGN(setting)	__ALIGN_MASK(setting, ~ICE_ITR_MASK)