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Commit 6fc8a65b authored by Linux Build Service Account's avatar Linux Build Service Account
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Merge 9fc82be7 on remote branch

Change-Id: I85cd7a3250d36330b883c863a635eaa7bf46ca45
parents 8ba01f22 9fc82be7
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+6 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ Optional properties:
- qcom,cmd-sync-wait-broadcast:		Boolean used to broadcast dcs command to panels.
- qcom,mdss-dsi-fbc-enable:		Boolean used to enable frame buffer compression mode.
- qcom,mdss-dsi-panel-mode-switch:	Boolean used to enable panel operating mode switch.
- qcom,poms-align-panel-vsync:		Boolean used to align panel TE with timing engine vsync in POMS
- qcom,mdss-dsi-fbc-slice-height:	Slice height(in lines) of compressed block.
					Expressed as power of 2. To set as 128 lines,
					this should be set to 7.
@@ -409,6 +410,9 @@ Optional properties:
- qcom,mdss-dsi-tx-eot-append:		Boolean used to enable appending end of transmission packets.
- qcom,ulps-enabled:			Boolean to enable support for Ultra Low Power State (ULPS) mode.
- qcom,suspend-ulps-enabled:		Boolean to enable support for ULPS mode for panels during suspend state.
- qcom,spr-pack-type:		    String to specify the SPR pack type of panel pixel layout
					Expected string for the pack types supported by MDSS are,
					"pentile", "rgbw", "yygm", "yygw"
- qcom,panel-roi-alignment:		Specifies the panel ROI alignment restrictions on its
					left, top, width, height alignments and minimum width and
					height values. This property is specified per timing node to support
@@ -615,6 +619,7 @@ Example:
		qcom,cmd-sync-wait-broadcast;
		qcom,mdss-dsi-fbc-enable;
		qcom,mdss-dsi-panel-mode-switch;
		qcom,poms-align-panel-vsync;
		qcom,mdss-dsi-fbc-slice-height = <5>;
		qcom,mdss-dsi-fbc-2d-pred-mode;
		qcom,mdss-dsi-fbc-ver2-mode;
@@ -650,6 +655,7 @@ Example:
		qcom,mdss-dsi-bl-max-level = < 15>;
		qcom,mdss-brightness-max-level = <255>;
		qcom,bl-update-flag = "delay_until_first_frame";
		qcom,spr-pack-type = "pentile";
		qcom,mdss-dsi-interleave-mode = <0>;
		qcom,mdss-dsi-panel-type = "dsi_video_mode";
		qcom,mdss-dsi-te-check-enable;

bindings/mdss-pll.txt

deleted100644 → 0
+0 −108
Original line number Diff line number Diff line
Qualcomm Technologies, Inc. MDSS pll for DSI/EDP/HDMI

mdss-pll is a pll controller device which supports pll devices that
are compatible with MIPI display serial interface specification,
HDMI and edp.

Required properties:
- compatible:		Compatible name used in the driver. Should be one of:
                        "qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939",
                        "qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994",
                        "qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909",
                        "qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994",
                        "qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992",
                        "qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996",
                        "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",
                        "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",
                        "qcom,mdss_edp_pll_8996_v3",  "qcom,mdss_edp_pll_8996_v3_1p8",
                        "qcom,mdss_dsi_pll_10nm",  "qcom,mdss_dp_pll_8998",
                        "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm",
                        "qcom,mdss_dsi_pll_7nm",   "qcom,mdss_dp_pll_7nm",
			"qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm",
			"qcom,mdss_dp_pll_14nm", "qcom,mdss_dsi_pll_7nm_v2",
			"qcom,mdss_hdmi_pll_28lpm","qcom,mdss_dsi_pll_7nm_v4_1",
			"qcom,mdss_dp_pll_7nm_v2"
- cell-index:		Specifies the controller used
- reg:			offset and length of the register set for the device.
- reg-names :		names to refer to register sets related to this device
- gdsc-supply:		Phandle for gdsc regulator device node.
- vddio-supply:		Phandle for vddio regulator device node.
- clocks:		List of Phandles for clock device nodes
			needed by the device.
- clock-names:		List of clock names needed by the device.
- clock-rate:		List of clock rates in Hz.

Optional properties:
- label:	       	A string used to describe the driver used.
- vcca-supply:		Phandle for vcca regulator device node.


- qcom,dsi-pll-ssc-en:	Boolean property to indicate that ssc is enabled.
- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread"
			or "center-spread". Default is "down-spread" if it is not specified.
- qcom,ssc-frequency-hz:	Integer property to specify the spread frequency
			to be programmed for the SSC.
- qcom,ssc-ppm:		Integer property to specify the Parts per Million
			value of SSC.

- qcom,platform-supply-entries:	A node that lists the elements of the supply. There
				can be more than one instance of this binding,
				in which case the entry would be appended with
				the supply entry index.
				e.g. qcom,platform-supply-entry@0
				- reg: offset and length of the register set for the device.
				-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
				-- qcom,supply-min-voltage: minimum voltage level (uV)
				-- qcom,supply-max-voltage: maximum voltage level (uV)
				-- qcom,supply-enable-load: load drawn (uA) from enabled supply
				-- qcom,supply-disable-load: load drawn (uA) from disabled supply
				-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
				-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
				-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
				-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off

Example:
	mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 {
		compatible = "qcom,mdss_dsi_pll_8974";
		label = "MDSS DSI 0 PLL";
		cell-index = <0>;

		reg = <0xfd922A00 0xD4>,
		      <0xfd922900 0x64>,
		      <0xfd8c2300 0x8>;
		reg-names = "pll_base", "dynamic_pll_base", "gdsc_base";
		gdsc-supply = <&gdsc_mdss>;
		vddio-supply = <&pm8941_l12>;
		vcca-supply = <&pm8941_l28>;

		clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,
			 <&clock_gcc clk_gcc_mdss_ahb_clk>,
			 <&clock_gcc clk_gcc_mdss_axi_clk>;
		clock-names = "mdp_core_clk", "iface_clk", "bus_clk";
		clock-rate = <0>, <0>, <0>;

		qcom,dsi-pll-slave;
		qcom,dsi-pll-ssc-en;
		qcom,dsi-pll-ssc-mode = "down-spread";
		qcom,ssc-frequency-hz = <30000>;
		qcom,ssc-ppm = <5000>;

		qcom,platform-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,platform-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vddio";
				qcom,supply-min-voltage = <1800000>;
				qcom,supply-max-voltage = <1800000>;
				qcom,supply-enable-load = <100000>;
				qcom,supply-disable-load = <100>;
				qcom,supply-pre-on-sleep = <0>;
				qcom,supply-post-on-sleep = <20>;
				qcom,supply-pre-off-sleep = <0>;
				qcom,supply-post-off-sleep = <0>;
			};
		};
	};

bindings/msm_hdcp.txt

0 → 100644
+14 −0
Original line number Diff line number Diff line
MSM HDCP driver

Standalone driver managing HDCP related communications
between TZ and HLOS for MSM chipset.

Required properties:

compatible = "qcom,msm-hdcp";

Example:

qcom_msmhdcp: qcom,msm_hdcp {
       compatible = "qcom,msm-hdcp";
};
+13 −3
Original line number Diff line number Diff line
@@ -3,17 +3,18 @@ Qualcomm Technologies, Inc.
mdss-dsi is the master DSI device which supports multiple DSI host controllers
that are compatible with MIPI display serial interface specification.

DSI Controller:
DSI Controller and PHY:
Required properties:
- compatible:           Should be "qcom,dsi-ctrl-hw-v<version>". Supported
			versions include 1.4, 2.0 and 2.2.
			eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0,
			qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3,
			qcom,dsi-ctrl-hw-v2.4
			qcom,dsi-ctrl-hw-v2.4, qcom,dsi-ctrl-hw-v2.5
			And for dsi phy driver:
			qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm,
			qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0,
			qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1
			qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0,
			qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2
- reg:                  Base address and length of DSI controller's memory
			mapped regions.
- reg-names:            A list of strings that name the list of regs.
@@ -32,6 +33,8 @@ Required properties:
			"core_clk"
			"byte_clk_rcg"
			"pixel_clk_rcg"
- pll-label             Supported versions of DSI PLL:
                        dsi_pll_5nm
- gdsc-supply:		phandle to gdsc regulator node.
- vdda-supply:		phandle to vdda regulator node.
- vcca-supply:		phandle to vcca regulator node.
@@ -116,3 +119,10 @@ Optional properties:
					specified in Documentation/devicetree/bindings/graph.txt.
					Video port 0 reg 0 is for the bridge output. The remote
					endpoint phandle should be mipi_dsi_device device node.
- qcom,dsi-pll-ssc-en:                  Boolean property to indicate that ssc is enabled.
- qcom,dsi-pll-ssc-mode:		Spread-spectrum clocking. It can be either "down-spread"
					or "center-spread". Default is "down-spread" if it is not specified.
- qcom,ssc-frequency-hz:		Integer property to specify the spread frequency
					to be programmed for the SSC.
- qcom,ssc-ppm:                         Integer property to specify the Parts per Million
					value of SSC.
+62 −84
Original line number Diff line number Diff line
@@ -223,19 +223,23 @@ Optional properties:
- qcom,sde-dsc-enc:		Array of offset addresses for the available dsc
				encoder blocks. These offsets are calculated from
				the corresponding DSC base.
- qcom,sde-dsc-enc-size		A u32 value indicates the enc block offset range.
- qcom,sde-dsc-ctl:		Array of offset addresses for the available dsc
				ctl blocks. These offsets are calculated from
				the corresponding DSC base.
- qcom,sde-dsc-ctl-size		A u32 value indicates the ctl block offset range.
- qcom,sde-dsc-native422-supp:	Array of flags indicating whether corresponding dsc
				block can support native 422 and native 420
				encoding.
- qcom,sde-vdc-off:		A u32 offset address for the available vdc blocks.
						This offset is calculated from register "mdp_phys"
						defined in reg property.
- qcom,sde-vdc-enc-size		A u32 value indicates the enc block offset range.
- qcom,sde-vdc-enc:		A u32 offset address for the vdc encoder block. This offset is
						calculated from qcom,sde-vdc-off.
- qcom,sde-vdc-ctl:		A u32 offset address for the vdc ctl block. This offset is
						calculated from qcom,sde-vdc-off.
- qcom,sde-vdc-ctl-size		A u32 value indicates the ctl block offset range.
- qcom,sde-qdss-off:		A u32 offset indicates the qdss block offset.
- qcom,sde-dither-off:		A u32 offset indicates the dither block offset on pingpong.
- qcom,sde-dither-version:	A u32 value indicates the dither block version.
@@ -315,6 +319,10 @@ Optional properties:
				corresponding DSPP base.
- qcom,sde-dspp-rc-size:	A u32 value indicating the RC block address range.
- qcom,sde-dspp-rc-mem-size:	A u32 value indicating the RC block shared memory size.
- qcom,sde-dspp-spr-off:    Array of u32 offsets indicate the SPR block offsets from the
                corresponding DSPP block offset as base.
- qcom,sde-dspp-spr-size:    A u32 value indicating the SPR block register address range
- qcom,sde-dspp-spr-version:    A u32 value indicating the version of SPR hardware.
- qcom,sde-vbif-id:		Array of vbif ids corresponding to the
				offsets defined in property: qcom,sde-vbif-off.
- qcom,sde-vbif-default-ot-rd-limit:	A u32 value indicates the default read OT limit
@@ -338,9 +346,11 @@ Optional properties:
				control register. Number of offsets defined should
				match the number of offsets defined in
				property: qcom,sde-wb-off
- qcom,sde-reg-dma-off:         Offset of the register dma hardware block from
				"regdma_phys" defined in reg property.
- qcom,sde-reg-dma-version:	Version of the reg dma hardware block.
- qcom,sde-reg-dma-off:         Array of u32 offset addresses of the dma hardware blocks,
				relative to "regdma_phys" defined in reg property.
- qcom,sde-reg-dma-id:		Array of u32 DMA block type ids corresponding to the
				offsets declared in property: qcom,sde-reg-dma-off
- qcom,sde-reg-dma-version:	Version of the reg dma hardware blocks.
- qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys"
				defined in reg property.
- qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast
@@ -416,51 +426,35 @@ Optional properties:
				priority for concurrent writeback clients.
- qcom,sde-vbif-qos-lutdma-remap:	This array is used to program vbif qos remapper register
				priority for lutdma client.
- qcom,sde-danger-lut:		Array of 5 cell property, with a format of
				<linear, tile, nrt, cwb, tile-qseed>,
				indicating the danger luts on sspp.
- qcom,sde-safe-lut-linear:	Array of 2 cell property, with a format of
				<fill level, lut> in ascending fill level
				indicating the safe luts for linear format on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-safe-lut-macrotile:	Array of 2 cell property, with a format of
				<fill level, lut> in ascending fill level
				indicating the safe luts for macrotile format on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-safe-lut-macrotile-qseed: Array of 2 cell property, with a format of
				<fill level, lut> in ascending fill level
				indicating the safe luts for macrotile format
				with qseed3 on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-safe-lut-nrt:	Array of 2 cell property, with a format of
				<fill level, lut> in ascending fill level
				indicating the safe luts for nrt (e.g wfd) on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-safe-lut-cwb:	Array of 2 cell property, with a format of
				<fill level, lut> in ascending fill level
				indicating the safe luts for cwb on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-qos-lut-linear:	Array of 3 cell property, with a format of
				<fill level, lut hi, lut lo> in ascending fill level
				indicating the qos luts for linear format on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-qos-lut-macrotile:	Array of 3 cell property, with a format of
				<fill level, lut hi, lut lo> in ascending fill level
				indicating the qos luts for macrotile format on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-qos-lut-macrotile-qseed: Array of 3 cell property, with a format of
				<fill level, lut hi, lut lo> in ascending fill level
				indicating the qos luts for macrotile format
				with qseed3 enabled on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-qos-lut-nrt:		Array of 3 cell property, with a format of
				<fill level, lut hi, lut lo> in ascending fill level
				indicating the qos luts for nrt (e.g wfd) on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-qos-lut-cwb:		Array of 3 cell property, with a format of
				<fill level, lut hi, lut lo> in ascending fill level
				indicating the qos luts for cwb on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-qos-refresh-rates:	A u32 array indicates danger, safe and creq luts
				qos configuration for different refresh rates.
- qcom,sde-danger-lut:		A u32 array of 6 cell property, with a format of
				<linear, tile, nrt, cwb, tile-qseed, linear-qseed>,
				indicating the danger luts on sspp and wb.
- qcom,sde-safe-lut:		A u32 array of 6 cell property, with a format of
				<linear, tile, nrt, cwb, tile-qseed, linear-qseed>,
				indicating the safe luts on sspp and wb.
- qcom,sde-qos-lut-linear:	A u64 array of 2 cell property, with a format of
				<lut hi, lut lo> in ascending fill level indicating
				the creq luts for linear format on sspp.
- qcom,sde-qos-lut-linear-qseed: A u64 array of 2 cell property, with a format of
				<lut hi, lut lo> in ascending fill level indicating
				the creq luts for linear format with qseed usage
				(scaling) on sspp.
- qcom,sde-qos-lut-macrotile:	A u64 array of 2 cell property, with a format of
				<lut hi, lut lo> in ascending fill level indicating
				the creq luts for macrotile format on sspp.
- qcom,sde-qos-lut-macrotile-qseed: A u64 array of 2 cell property, with a format of
				<lut hi, lut lo> in ascending fill level
				indicating the creq luts for macrotile format
				with qseed enabled (scaling enabled) on sspp.
- qcom,sde-qos-lut-nrt:		A u64 array of 2 cell property, with a format of
				<lut hi, lut lo> in ascending fill level
				indicating the creq luts for nrt (e.g wfd) on sspp
				and wb.
- qcom,sde-qos-lut-cwb:		A u64 array of 2 cell property, with a format of
				<lut hi, lut lo> in ascending fill level
				indicating the creq luts for cwb on sspp.
- qcom,sde-cdp-setting:		Array of 2 cell property, with a format of
				<read enable, write enable> for cdp use cases in
				order of <real_time>, and <non_real_time>.
@@ -608,6 +602,9 @@ Example:
    qcom,sde-dspp-rc-version = <0x00010000>;
    qcom,sde-dspp-rc-off = <0x15800 0x14c00>;
    qcom,sde-dspp-rc-size = <0x100>;
    qcom,sde-dspp-spr-off = <0x15400 0x14400>;
    qcom,sde-dspp-spr-size = <0x200>;
    qcom,sde-dspp-spr-version = <0x00010000>:
    qcom,sde-dspp-rc-mem-size = <2720>;
    qcom,sde-dest-scaler-top-off = <0x00061000>;
    qcom,sde-dest-scaler-off = <0x800 0x1000>;
@@ -718,40 +715,20 @@ Example:
    qcom,sde-wb-id = <2>;
    qcom,sde-wb-clk-ctrl = <0x2bc 16>;

    qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000
            0x00000000 0x0000ffff>;
    qcom,sde-safe-lut-linear = <0 0xfff8>;
    qcom,sde-safe-lut-macrotile = <0 0xf000>;
    qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>;
    qcom,sde-safe-lut-nrt = <0 0xffff>;
    qcom,sde-safe-lut-cwb = <0 0xffff>;

    qcom,sde-qos-lut-linear =
            <4 0x00000000 0x00000357>,
            <5 0x00000000 0x00003357>,
            <6 0x00000000 0x00023357>,
            <7 0x00000000 0x00223357>,
            <8 0x00000000 0x02223357>,
            <9 0x00000000 0x22223357>,
            <10 0x00000002 0x22223357>,
            <11 0x00000022 0x22223357>,
            <12 0x00000222 0x22223357>,
            <13 0x00002222 0x22223357>,
            <14 0x00012222 0x22223357>,
            <0 0x00112222 0x22223357>;
    qcom,sde-qos-lut-macrotile =
            <10 0x00000003 0x44556677>,
            <11 0x00000033 0x44556677>,
            <12 0x00000233 0x44556677>,
            <13 0x00002233 0x44556677>,
            <14 0x00012233 0x44556677>,
            <0 0x00112233 0x44556677>;
    qcom,sde-qos-lut-macrotile-qseed =
            <0 0x00112233 0x66777777>;
    qcom,sde-qos-lut-nrt =
            <0 0x00000000 0x00000000>;
    qcom,sde-qos-lut-cwb =
            <0 0x75300000 0x00000000>;
    qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000
		0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff
		0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>;

    qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>,
		<0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>;

    qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
    qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
    qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
    qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
    qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>;
    qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>;
    qcom,sde-qos-refresh-rates = <60 120>;

    qcom,sde-cdp-setting = <1 1>, <1 0>;

@@ -802,8 +779,9 @@ Example:
    qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
    qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;

    qcom,sde-reg-dma-off = <0>;
    qcom,sde-reg-dma-version = <0x00010002>;
    qcom,sde-reg-dma-off = <0 0x400>;
    qcom,sde-reg-dma-id = <0 1>;
    qcom,sde-reg-dma-version = <0x00020000>;
    qcom,sde-reg-dma-trigger-off = <0x119c>;
    qcom,sde-reg-dma-broadcast-disabled = <0>;
    qcom,sde-reg-dma-xin-id = <7>;
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