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Commit 6fc11b0e authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: refine vce3.0 code and related powerplay pg code. 



1. not start vce3.0 when hw_init
2. stop vce3.0 when vce idle.
3. pg mask used to ctrl power down/up vce.
4. change cg pg sequence in powerplay.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f1ea278d

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

+6 −11
Original line number Diff line number Diff line
@@ -230,10 +230,6 @@ static int vce_v3_0_start(struct amdgpu_device *adev) 
	struct amdgpu_ring *ring;

	int idx, r;



	vce_v3_0_override_vce_clock_gating(adev, true);

	if (!(adev->flags & AMD_IS_APU))

		amdgpu_asic_set_vce_clocks(adev, 10000, 10000);



	ring = &adev->vce.ring[0];

	WREG32(mmVCE_RB_RPTR, ring->wptr);

	WREG32(mmVCE_RB_WPTR, ring->wptr);
@@ -436,9 +432,9 @@ static int vce_v3_0_hw_init(void *handle) 
	int r, i;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	r = vce_v3_0_start(adev);

	if (r)

		return r;

	vce_v3_0_override_vce_clock_gating(adev, true);

	if (!(adev->flags & AMD_IS_APU))

		amdgpu_asic_set_vce_clocks(adev, 10000, 10000);



	for (i = 0; i < adev->vce.num_rings; i++)

		adev->vce.ring[i].ready = false;
@@ -766,12 +762,11 @@ static int vce_v3_0_set_powergating_state(void *handle, 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int ret = 0;



	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))

		return 0;



	if (state == AMD_PG_STATE_GATE) {

		ret = vce_v3_0_stop(adev);

		if (ret)

			goto out;

		adev->vce.is_powergated = true;

		/* XXX do we need a vce_v3_0_stop()? */

	} else {

		ret = vce_v3_0_start(adev);

		if (ret)

drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c

+23 −36
Original line number Diff line number Diff line
@@ -190,46 +190,33 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) 
{

	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);



	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,

					PHM_PlatformCaps_VCEPowerGating)) {

		if (cz_hwmgr->vce_power_gated != bgate) {

	if (bgate) {

				cgs_set_clockgating_state(

							hwmgr->device,

							AMD_IP_BLOCK_TYPE_VCE,

							AMD_CG_STATE_GATE);

		cgs_set_powergating_state(

					hwmgr->device,

					AMD_IP_BLOCK_TYPE_VCE,

					AMD_PG_STATE_GATE);

		cgs_set_clockgating_state(

					hwmgr->device,

					AMD_IP_BLOCK_TYPE_VCE,

					AMD_CG_STATE_GATE);

		cz_enable_disable_vce_dpm(hwmgr, false);

		cz_dpm_powerdown_vce(hwmgr);

		cz_hwmgr->vce_power_gated = true;

	} else {

		cz_dpm_powerup_vce(hwmgr);

		cz_hwmgr->vce_power_gated = false;

				cgs_set_powergating_state(

							hwmgr->device,

							AMD_IP_BLOCK_TYPE_VCE,

							AMD_CG_STATE_UNGATE);

		cgs_set_clockgating_state(

					hwmgr->device,

					AMD_IP_BLOCK_TYPE_VCE,

					AMD_PG_STATE_UNGATE);

		cgs_set_powergating_state(

					hwmgr->device,

					AMD_IP_BLOCK_TYPE_VCE,

					AMD_CG_STATE_UNGATE);

		cz_dpm_update_vce_dpm(hwmgr);

		cz_enable_disable_vce_dpm(hwmgr, true);

		return 0;

	}

		}

	} else {

		cz_hwmgr->vce_power_gated = bgate;

		cz_dpm_update_vce_dpm(hwmgr);

		cz_enable_disable_vce_dpm(hwmgr, !bgate);

		return 0;

	}



	if (!cz_hwmgr->vce_power_gated)

		cz_dpm_update_vce_dpm(hwmgr);



	return 0;

}

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c

+7 −4
Original line number Diff line number Diff line
@@ -173,12 +173,12 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) 
{

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);



	if (data->vce_power_gated == bgate)

		return 0;



	data->vce_power_gated = bgate;



	if (bgate) {

		cgs_set_powergating_state(hwmgr->device,

						AMD_IP_BLOCK_TYPE_VCE,

						AMD_PG_STATE_UNGATE);

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_VCE,

				AMD_CG_STATE_GATE);
@@ -186,10 +186,13 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) 
		smu7_powerdown_vce(hwmgr);

	} else {

		smu7_powerup_vce(hwmgr);

		smu7_update_vce_dpm(hwmgr, false);

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_VCE,

				AMD_CG_STATE_UNGATE);

		cgs_set_powergating_state(hwmgr->device,

						AMD_IP_BLOCK_TYPE_VCE,

						AMD_PG_STATE_UNGATE);

		smu7_update_vce_dpm(hwmgr, false);

	}

	return 0;

}