[MIPS] PMC MSP71xx PCI support (6f95e60a) · Commits · e / devices / android_kernel_fairphone_FP5

arch/mips/pci/Makefile

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		@@ -32,6 +32,9 @@ obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o
		obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
		obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
		obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o
		obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
		obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
		obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
		obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
		pci-yosemite.o
		obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o

arch/mips/pci/fixup-pmcmsp.c

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		/*
		* PMC-Sierra MSP board specific pci fixups.
		*
		* Copyright 2001 MontaVista Software Inc.
		* Copyright 2005-2007 PMC-Sierra, Inc
		*
		* Author: MontaVista Software, Inc.
		* ppopov@mvista.com or source@mvista.com
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of the GNU General Public License as published by the
		* Free Software Foundation; either version 2 of the License, or (at your
		* option) any later version.
		*
		* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
		* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
		* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
		* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
		* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
		* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
		* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
		* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
		* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		*
		* You should have received a copy of the GNU General Public License along
		* with this program; if not, write to the Free Software Foundation, Inc.,
		* 675 Mass Ave, Cambridge, MA 02139, USA.
		*/

		#ifdef CONFIG_PCI

		#include <linux/types.h>
		#include <linux/pci.h>
		#include <linux/kernel.h>
		#include <linux/init.h>

		#include <asm/byteorder.h>

		#include <msp_pci.h>
		#include <msp_cic_int.h>

		/* PCI interrupt pins */
		#define IRQ4 MSP_INT_EXT4
		#define IRQ5 MSP_INT_EXT5
		#define IRQ6 MSP_INT_EXT6

		#if defined(CONFIG_PMC_MSP7120_GW)
		/* Garibaldi Board IRQ wiring to PCI slots */
		static char irq_tab[][5] __initdata = {
		/* INTA INTB INTC INTD */
		{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
		{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
		{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
		{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
		{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
		{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
		{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
		{0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
		{0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
		{0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
		{0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
		{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
		{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
		{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
		{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
		{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
		{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
		{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
		{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
		{0, IRQ4, IRQ4, 0, 0 }, /* 18 (AD[28]): slot 0 */
		{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
		{0, IRQ5, IRQ5, 0, 0 }, /* 20 (AD[30]): slot 1 */
		{0, IRQ6, IRQ6, 0, 0 } /* 21 (AD[31]): slot 2 */
		};

		#elif defined(CONFIG_PMC_MSP7120_EVAL)

		/* MSP7120 Eval Board IRQ wiring to PCI slots */
		static char irq_tab[][5] __initdata = {
		/* INTA INTB INTC INTD */
		{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
		{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
		{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
		{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
		{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
		{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
		{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
		{0, IRQ6, IRQ6, 0, 0 }, /* 6 (AD[16]): slot 3 (mini) */
		{0, IRQ5, IRQ5, 0, 0 }, /* 7 (AD[17]): slot 2 (mini) */
		{0, IRQ4, IRQ4, IRQ4, IRQ4}, /* 8 (AD[18]): slot 0 (PCI) */
		{0, IRQ5, IRQ5, IRQ5, IRQ5}, /* 9 (AD[19]): slot 1 (PCI) */
		{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
		{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
		{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
		{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
		{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
		{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
		{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
		{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
		{0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
		{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
		{0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
		{0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
		};

		#else

		/* Unknown board -- don't assign any IRQs */
		static char irq_tab[][5] __initdata = {
		/* INTA INTB INTC INTD */
		{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
		{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
		{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
		{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
		{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
		{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
		{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
		{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
		{0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
		{0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
		{0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
		{0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
		{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
		{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
		{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
		{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
		{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
		{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
		{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
		{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
		{0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
		{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
		{0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
		{0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
		};
		#endif

		/*****************************************************************************
		*
		* FUNCTION: pcibios_plat_dev_init
		* _________________________________________________________________________
		*
		* DESCRIPTION: Perform platform specific device initialization at
		* pci_enable_device() time.
		* None are needed for the MSP7120 PCI Controller.
		*
		* INPUTS: dev - structure describing the PCI device
		*
		* OUTPUTS: none
		*
		* RETURNS: PCIBIOS_SUCCESSFUL
		*
		****************************************************************************/
		int pcibios_plat_dev_init(struct pci_dev *dev)
		{
		return PCIBIOS_SUCCESSFUL;
		}

		/*****************************************************************************
		*
		* FUNCTION: pcibios_map_irq
		* _________________________________________________________________________
		*
		* DESCRIPTION: Perform board supplied PCI IRQ mapping routine.
		*
		* INPUTS: dev - unused
		* slot - PCI slot. Identified by which bit of the AD[] bus
		* drives the IDSEL line. AD[10] is 0, AD[31] is
		* slot 21.
		* pin - numbered using the scheme of the PCI_INTERRUPT_PIN
		* field of the config header.
		*
		* OUTPUTS: none
		*
		* RETURNS: IRQ number
		*
		****************************************************************************/
		int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
		{
		#if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL)
		printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n");
		#endif
		printk(KERN_WARNING "PCI: irq_tab returned %d for slot=%d pin=%d\n",
		irq_tab[slot][pin], slot, pin);

		return irq_tab[slot][pin];
		}

		#endif /* CONFIG_PCI */

arch/mips/pci/ops-pmcmsp.c

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arch/mips/pmc-sierra/msp71xx/msp_pci.c

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		/*
		* The setup file for PCI related hardware on PMC-Sierra MSP processors.
		*
		* Copyright 2005-2006 PMC-Sierra, Inc.
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of the GNU General Public License as published by the
		* Free Software Foundation; either version 2 of the License, or (at your
		* option) any later version.
		*
		* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
		* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
		* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
		* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
		* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
		* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
		* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
		* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
		* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		*
		* You should have received a copy of the GNU General Public License along
		* with this program; if not, write to the Free Software Foundation, Inc.,
		* 675 Mass Ave, Cambridge, MA 02139, USA.
		*/

		#include <linux/init.h>

		#include <msp_prom.h>
		#include <msp_regs.h>

		extern void msp_pci_init(void);

		static int __init msp_pci_setup(void)
		{
		#if 0 /* Linux 2.6 initialization code to be completed */
		if (getdeviceid() & DEV_ID_SINGLE_PC) {
		/* If single card mode */
		slmRegs sreg = (slmRegs ) SREG_BASE;

		sreg->single_pc_enable = SINGLE_PCCARD;
		}
		#endif

		msp_pci_init();

		return 0;
		}

		subsys_initcall(msp_pci_setup);

include/asm-mips/pmc-sierra/msp71xx/msp_pci.h

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		/*
		* Copyright (c) 2000-2006 PMC-Sierra INC.
		*
		* This program is free software; you can redistribute it
		* and/or modify it under the terms of the GNU General
		* Public License as published by the Free Software
		* Foundation; either version 2 of the License, or (at your
		* option) any later version.
		*
		* This program is distributed in the hope that it will be
		* useful, but WITHOUT ANY WARRANTY; without even the implied
		* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
		* PURPOSE. See the GNU General Public License for more
		* details.
		*
		* You should have received a copy of the GNU General Public
		* License along with this program; if not, write to the Free
		* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
		* 02139, USA.
		*
		* PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
		* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
		* SOFTWARE.
		*/

		#ifndef _MSP_PCI_H_
		#define _MSP_PCI_H_

		#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))

		/*
		* It is convenient to program the OATRAN register so that
		* Athena virtual address space and PCI address space are
		* the same. This is not a requirement, just a convenience.
		*
		* The only hard restrictions on the value of OATRAN is that
		* OATRAN must not be programmed to allow translated memory
		* addresses to fall within the lowest 512MB of
		* PCI address space. This region is hardcoded
		* for use as Athena PCI Host Controller target
		* access memory space to the Athena's SDRAM.
		*
		* Note that OATRAN applies only to memory accesses, not
		* to I/O accesses.
		*
		* To program OATRAN to make Athena virtual address space
		* and PCI address space have the same values, OATRAN
		* is to be programmed to 0xB8000000. The top seven
		* bits of the value mimic the seven bits clipped off
		* by the PCI Host controller.
		*
		* With OATRAN at the said value, when the CPU does
		* an access to its virtual address at, say 0xB900_5000,
		* the address appearing on the PCI bus will be
		* 0xB900_5000.
		* - Michael Penner
		*/
		#define MSP_PCI_OATRAN 0xB8000000UL

		#define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL)
		#define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000)
		#define MSP_PCI_SPACE_END \
		(MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
		#define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL)
		#define MSP_PCI_IOSPACE_SIZE 0x1000
		#define MSP_PCI_IOSPACE_END \
		(MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)

		/* IRQ for PCI status interrupts */
		#define PCI_STAT_IRQ 20

		#define QFLUSH_REG_1 0xB7F40000

		typedef volatile unsigned int pcireg;
		typedef void * volatile ppcireg;

		struct pci_block_copy
		{
		pcireg unused1; /* +0x00 */
		pcireg unused2; /* +0x04 */
		ppcireg unused3; /* +0x08 */
		ppcireg unused4; /* +0x0C */
		pcireg unused5; /* +0x10 */
		pcireg unused6; /* +0x14 */
		pcireg unused7; /* +0x18 */
		ppcireg unused8; /* +0x1C */
		ppcireg unused9; /* +0x20 */
		pcireg unusedA; /* +0x24 */
		ppcireg unusedB; /* +0x28 */
		ppcireg unusedC; /* +0x2C */
		};

		enum
		{
		config_device_vendor, /* 0 */
		config_status_command, /* 1 */
		config_class_revision, /* 2 */
		config_BIST_header_latency_cache, /* 3 */
		config_BAR0, /* 4 */
		config_BAR1, /* 5 */
		config_BAR2, /* 6 */
		config_not_used7, /* 7 */
		config_not_used8, /* 8 */
		config_not_used9, /* 9 */
		config_CIS, /* 10 */
		config_subsystem, /* 11 */
		config_not_used12, /* 12 */
		config_capabilities, /* 13 */
		config_not_used14, /* 14 */
		config_lat_grant_irq, /* 15 */
		config_message_control,/* 16 */
		config_message_addr, /* 17 */
		config_message_data, /* 18 */
		config_VPD_addr, /* 19 */
		config_VPD_data, /* 20 */
		config_maxregs /* 21 - number of registers */
		};

		struct msp_pci_regs
		{
		pcireg hop_unused_00; /* +0x00 */
		pcireg hop_unused_04; /* +0x04 */
		pcireg hop_unused_08; /* +0x08 */
		pcireg hop_unused_0C; /* +0x0C */
		pcireg hop_unused_10; /* +0x10 */
		pcireg hop_unused_14; /* +0x14 */
		pcireg hop_unused_18; /* +0x18 */
		pcireg hop_unused_1C; /* +0x1C */
		pcireg hop_unused_20; /* +0x20 */
		pcireg hop_unused_24; /* +0x24 */
		pcireg hop_unused_28; /* +0x28 */
		pcireg hop_unused_2C; /* +0x2C */
		pcireg hop_unused_30; /* +0x30 */
		pcireg hop_unused_34; /* +0x34 */
		pcireg if_control; /* +0x38 */
		pcireg oatran; /* +0x3C */
		pcireg reset_ctl; /* +0x40 */
		pcireg config_addr; /* +0x44 */
		pcireg hop_unused_48; /* +0x48 */
		pcireg msg_signaled_int_status; /* +0x4C */
		pcireg msg_signaled_int_mask; /* +0x50 */
		pcireg if_status; /* +0x54 */
		pcireg if_mask; /* +0x58 */
		pcireg hop_unused_5C; /* +0x5C */
		pcireg hop_unused_60; /* +0x60 */
		pcireg hop_unused_64; /* +0x64 */
		pcireg hop_unused_68; /* +0x68 */
		pcireg hop_unused_6C; /* +0x6C */
		pcireg hop_unused_70; /* +0x70 */

		struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));

		pcireg error_hdr1; /* +0xE0 */
		pcireg error_hdr2; /* +0xE4 */

		pcireg config[config_maxregs] __attribute__((aligned(256)));

		};

		#define BPCI_CFGADDR_BUSNUM_SHF 16
		#define BPCI_CFGADDR_FUNCTNUM_SHF 8
		#define BPCI_CFGADDR_REGNUM_SHF 2
		#define BPCI_CFGADDR_ENABLE (1<<31)

		#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
		#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
		#define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */
		#define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */
		#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
		#define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */
		#define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */

		#define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */
		#define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */
		#define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */
		#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
		#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
		#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
		#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
		#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
		#define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */
		#define BPCI_IFSTATUS_SER (1<<19) /* System error */
		#define BPCI_IFSTATUS_PER (1<<20) /* Parity error */
		#define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */
		#define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */
		#define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */
		#define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */
		#define BPCI_IFSTATUS_TA (1<<28) /* Target abort */
		#define BPCI_IFSTATUS_MA (1<<29) /* Master abort */
		#define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */
		#define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */

		#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */
		#define BPCI_RESETCTL_RT (1<<4) /* Release time */
		#define BPCI_RESETCTL_CT (1<<8) /* Config time */
		#define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */
		#define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */
		#define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */

		extern struct msp_pci_regs msp_pci_regs
		__attribute__((section(".register")));
		extern unsigned long msp_pci_config_space
		__attribute__((section(".register")));

		#endif /* !_MSP_PCI_H_ */