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Commit 6f92a654 authored by Rahul Lakkireddy's avatar Rahul Lakkireddy Committed by David S. Miller
Browse files

cxgb4: collect hardware misc dumps 



Collect path mtu, PM stats, TP clock info, congestion control, and VPD
data dumps.

Signed-off-by: default avatarRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: default avatarGanesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 08c4901b

drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h

+36 −0
Original line number Diff line number Diff line
@@ -49,6 +49,13 @@ struct cudbg_rss_vf_conf { 
	u32 rss_vf_vfh;

};



struct cudbg_pm_stats {

	u32 tx_cnt[T6_PM_NSTATS];

	u32 rx_cnt[T6_PM_NSTATS];

	u64 tx_cyc[T6_PM_NSTATS];

	u64 rx_cyc[T6_PM_NSTATS];

};



struct cudbg_hw_sched {

	u32 kbps[NTX_SCHED];

	u32 ipg[NTX_SCHED];
@@ -85,6 +92,22 @@ struct cudbg_cim_pif_la { 
	u8 data[0];

};



struct cudbg_clk_info {

	u64 retransmit_min;

	u64 retransmit_max;

	u64 persist_timer_min;

	u64 persist_timer_max;

	u64 keepalive_idle_timer;

	u64 keepalive_interval;

	u64 initial_srtt;

	u64 finwait2_timer;

	u32 dack_timer;

	u32 res;

	u32 cclk_ps;

	u32 tre;

	u32 dack_re;

};



struct cudbg_tid_info_region {

	u32 ntids;

	u32 nstids;
@@ -143,6 +166,19 @@ struct cudbg_mps_tcam { 
	u8 reserved[2];

};



struct cudbg_vpd_data {

	u8 sn[SERNUM_LEN + 1];

	u8 bn[PN_LEN + 1];

	u8 na[MACADDR_LEN + 1];

	u8 mn[ID_LEN + 1];

	u16 fw_major;

	u16 fw_minor;

	u16 fw_micro;

	u16 fw_build;

	u32 scfg_vers;

	u32 vpd_vers;

};



#define CUDBG_NUM_ULPTX 11

#define CUDBG_NUM_ULPTX_READ 512

drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h

+5 −0
Original line number Diff line number Diff line
@@ -49,18 +49,23 @@ enum cudbg_dbg_entity_type { 
	CUDBG_EDC1 = 19,

	CUDBG_RSS = 22,

	CUDBG_RSS_VF_CONF = 25,

	CUDBG_PATH_MTU = 27,

	CUDBG_PM_STATS = 30,

	CUDBG_HW_SCHED = 31,

	CUDBG_TP_INDIRECT = 36,

	CUDBG_SGE_INDIRECT = 37,

	CUDBG_ULPRX_LA = 41,

	CUDBG_TP_LA = 43,

	CUDBG_CIM_PIF_LA = 45,

	CUDBG_CLK = 46,

	CUDBG_CIM_OBQ_RXQ0 = 47,

	CUDBG_CIM_OBQ_RXQ1 = 48,

	CUDBG_PCIE_INDIRECT = 50,

	CUDBG_PM_INDIRECT = 51,

	CUDBG_TID_INFO = 54,

	CUDBG_MPS_TCAM = 57,

	CUDBG_VPD_DATA = 58,

	CUDBG_CCTRL = 60,

	CUDBG_MA_INDIRECT = 61,

	CUDBG_ULPTX_LA = 62,

	CUDBG_UP_CIM_INDIRECT = 64,

drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c

+135 −0
Original line number Diff line number Diff line
@@ -574,6 +574,44 @@ int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init, 
	return rc;

}



int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err)

{

	struct adapter *padap = pdbg_init->adap;

	struct cudbg_buffer temp_buff = { 0 };

	int rc;



	rc = cudbg_get_buff(dbg_buff, NMTUS * sizeof(u16), &temp_buff);

	if (rc)

		return rc;



	t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL);

	cudbg_write_and_release_buff(&temp_buff, dbg_buff);

	return rc;

}



int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err)

{

	struct adapter *padap = pdbg_init->adap;

	struct cudbg_buffer temp_buff = { 0 };

	struct cudbg_pm_stats *pm_stats_buff;

	int rc;



	rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_pm_stats),

			    &temp_buff);

	if (rc)

		return rc;



	pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data;

	t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc);

	t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc);

	cudbg_write_and_release_buff(&temp_buff, dbg_buff);

	return rc;

}



int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err)
@@ -813,6 +851,55 @@ int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init, 
	return rc;

}



int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err)

{

	struct adapter *padap = pdbg_init->adap;

	struct cudbg_buffer temp_buff = { 0 };

	struct cudbg_clk_info *clk_info_buff;

	u64 tp_tick_us;

	int rc;



	if (!padap->params.vpd.cclk)

		return CUDBG_STATUS_CCLK_NOT_DEFINED;



	rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_clk_info),

			    &temp_buff);

	if (rc)

		return rc;



	clk_info_buff = (struct cudbg_clk_info *)temp_buff.data;

	clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */

	clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A);

	clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res);

	clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res);

	tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000;



	clk_info_buff->dack_timer =

		(clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 *

		t4_read_reg(padap, TP_DACK_TIMER_A);

	clk_info_buff->retransmit_min =

		tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A);

	clk_info_buff->retransmit_max =

		tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A);

	clk_info_buff->persist_timer_min =

		tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A);

	clk_info_buff->persist_timer_max =

		tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A);

	clk_info_buff->keepalive_idle_timer =

		tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A);

	clk_info_buff->keepalive_interval =

		tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A);

	clk_info_buff->initial_srtt =

		tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A));

	clk_info_buff->finwait2_timer =

		tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A);



	cudbg_write_and_release_buff(&temp_buff, dbg_buff);

	return rc;

}



int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,

				struct cudbg_buffer *dbg_buff,

				struct cudbg_error *cudbg_err)
@@ -1196,6 +1283,54 @@ int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init, 
	return rc;

}



int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err)

{

	struct adapter *padap = pdbg_init->adap;

	struct cudbg_buffer temp_buff = { 0 };

	struct cudbg_vpd_data *vpd_data;

	int rc;



	rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_vpd_data),

			    &temp_buff);

	if (rc)

		return rc;



	vpd_data = (struct cudbg_vpd_data *)temp_buff.data;

	memcpy(vpd_data->sn, padap->params.vpd.sn, SERNUM_LEN + 1);

	memcpy(vpd_data->bn, padap->params.vpd.pn, PN_LEN + 1);

	memcpy(vpd_data->na, padap->params.vpd.na, MACADDR_LEN + 1);

	memcpy(vpd_data->mn, padap->params.vpd.id, ID_LEN + 1);

	vpd_data->scfg_vers = padap->params.scfg_vers;

	vpd_data->vpd_vers = padap->params.vpd_vers;

	vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(padap->params.fw_vers);

	vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(padap->params.fw_vers);

	vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(padap->params.fw_vers);

	vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(padap->params.fw_vers);

	cudbg_write_and_release_buff(&temp_buff, dbg_buff);

	return rc;

}



int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,

			struct cudbg_buffer *dbg_buff,

			struct cudbg_error *cudbg_err)

{

	struct adapter *padap = pdbg_init->adap;

	struct cudbg_buffer temp_buff = { 0 };

	u32 size;

	int rc;



	size = sizeof(u16) * NMTUS * NCCTRL_WIN;

	rc = cudbg_get_buff(dbg_buff, size, &temp_buff);

	if (rc)

		return rc;



	t4_read_cong_tbl(padap, (void *)temp_buff.data);

	cudbg_write_and_release_buff(&temp_buff, dbg_buff);

	return rc;

}



int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,

			      struct cudbg_buffer *dbg_buff,

			      struct cudbg_error *cudbg_err)

drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h

+15 −0
Original line number Diff line number Diff line
@@ -84,6 +84,12 @@ int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init, 
int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,

			      struct cudbg_buffer *dbg_buff,

			      struct cudbg_error *cudbg_err);

int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err);

int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err);

int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err);
@@ -99,6 +105,9 @@ int cudbg_collect_tp_la(struct cudbg_init *pdbg_init, 
int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,

			     struct cudbg_buffer *dbg_buff,

			     struct cudbg_error *cudbg_err);

int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err);

int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init,

				struct cudbg_buffer *dbg_buff,

				struct cudbg_error *cudbg_err);
@@ -117,6 +126,12 @@ int cudbg_collect_tid(struct cudbg_init *pdbg_init, 
int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err);

int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err);

int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,

			struct cudbg_buffer *dbg_buff,

			struct cudbg_error *cudbg_err);

int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,

			      struct cudbg_buffer *dbg_buff,

			      struct cudbg_error *cudbg_err);

drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c

+20 −0
Original line number Diff line number Diff line
@@ -46,18 +46,23 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = { 
	{ CUDBG_CIM_OBQ_NCSI, cudbg_collect_cim_obq_ncsi },

	{ CUDBG_RSS, cudbg_collect_rss },

	{ CUDBG_RSS_VF_CONF, cudbg_collect_rss_vf_config },

	{ CUDBG_PATH_MTU, cudbg_collect_path_mtu },

	{ CUDBG_PM_STATS, cudbg_collect_pm_stats },

	{ CUDBG_HW_SCHED, cudbg_collect_hw_sched },

	{ CUDBG_TP_INDIRECT, cudbg_collect_tp_indirect },

	{ CUDBG_SGE_INDIRECT, cudbg_collect_sge_indirect },

	{ CUDBG_ULPRX_LA, cudbg_collect_ulprx_la },

	{ CUDBG_TP_LA, cudbg_collect_tp_la },

	{ CUDBG_CIM_PIF_LA, cudbg_collect_cim_pif_la },

	{ CUDBG_CLK, cudbg_collect_clk_info },

	{ CUDBG_CIM_OBQ_RXQ0, cudbg_collect_obq_sge_rx_q0 },

	{ CUDBG_CIM_OBQ_RXQ1, cudbg_collect_obq_sge_rx_q1 },

	{ CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect },

	{ CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect },

	{ CUDBG_TID_INFO, cudbg_collect_tid },

	{ CUDBG_MPS_TCAM, cudbg_collect_mps_tcam },

	{ CUDBG_VPD_DATA, cudbg_collect_vpd_data },

	{ CUDBG_CCTRL, cudbg_collect_cctrl },

	{ CUDBG_MA_INDIRECT, cudbg_collect_ma_indirect },

	{ CUDBG_ULPTX_LA, cudbg_collect_ulptx_la },

	{ CUDBG_UP_CIM_INDIRECT, cudbg_collect_up_cim_indirect },
@@ -157,6 +162,12 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity) 
		len = adap->params.arch.vfcount *

		      sizeof(struct cudbg_rss_vf_conf);

		break;

	case CUDBG_PATH_MTU:

		len = NMTUS * sizeof(u16);

		break;

	case CUDBG_PM_STATS:

		len = sizeof(struct cudbg_pm_stats);

		break;

	case CUDBG_HW_SCHED:

		len = sizeof(struct cudbg_hw_sched);

		break;
@@ -191,6 +202,9 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity) 
		len = sizeof(struct cudbg_cim_pif_la);

		len += 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);

		break;

	case CUDBG_CLK:

		len = sizeof(struct cudbg_clk_info);

		break;

	case CUDBG_PCIE_INDIRECT:

		n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32));

		len = sizeof(struct ireg_buf) * n * 2;
@@ -206,6 +220,12 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity) 
		len = sizeof(struct cudbg_mps_tcam) *

		      adap->params.arch.mps_tcam_size;

		break;

	case CUDBG_VPD_DATA:

		len = sizeof(struct cudbg_vpd_data);

		break;

	case CUDBG_CCTRL:

		len = sizeof(u16) * NMTUS * NCCTRL_WIN;

		break;

	case CUDBG_MA_INDIRECT:

		if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {

			n = sizeof(t6_ma_ireg_array) /