ARM: dts: msm: Enable PCIe RC on sdxnightjar

&soc {

	pcie0: qcom,pcie@80000 {

		compatible = "qcom,pci-msm";

		reg = <0x80000 0x2000>,

			<0x86000 0x1000>,

			<0x40000000 0xf1d>,

			<0x40000f20 0xa8>,

			<0x40100000 0x100000>,

			<0x01956044 0x4>;

		reg-names = "parf", "phy", "dm_core", "elbi", "conf", "tcsr";

		cell-index = <0>;

		linux,pci-domain = <0>;

		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,

			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1d00000>;

		interrupt-parent = <&pcie0>;

		interrupts = <0 1 2 3 4>;

		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",

				"int_d";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0xffffffff>;

		interrupt-map = <0 0 0 0 &intc GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH

				0 0 0 1 &intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH

				0 0 0 2 &intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH

				0 0 0 3 &intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH

				0 0 0 4 &intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

		msi-parent = <&pcie0_msi>;

		perst-gpio = <&tlmm_pinmux 60 0>;

		wake-gpio = <&tlmm_pinmux 61 0>;

		pinctrl-names = "default";

		pinctrl-0 = <&pcie0_clkreq_default

			&pcie0_perst_default

			&pcie0_wake_default>;

		gdsc-vdd-supply = <&gdsc_pcie>;

		vreg-1p8-supply = <&pmd9650_l5>;

		vreg-0p9-supply = <&pmd9650_l4>;

		qcom,vreg-0.9-voltage-level = <928000 928000 24000>;

		interconnect-names = "icc_path";

		interconnects = <&system_noc MASTER_PCIE &bimc SLAVE_EBI_CH0>;

		clocks = <&gcc GCC_PCIE_PIPE_CLK>,

			<&rpmcc RPM_SMD_LN_BB_CLK>,

			<&gcc GCC_PCIE_SLEEP_CLK>,

			<&gcc GCC_PCIE_CFG_AHB_CLK>,

			<&gcc GCC_PCIE_AXI_MSTR_CLK>,

			<&gcc GCC_PCIE_AXI_CLK>,

			<&gcc GCC_PCIE_REF_CLK>;

		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",

				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",

				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",

				"pcie_0_ldo";

		max-clock-frequency-hz = <0>, <0>, <19200000>,

					<0>, <0>, <0>, <0>, <0>;

		resets = <&gcc GCC_PCIE_PHY_BCR>,

				<&gcc GCC_PCIEPHY_PHY_BCR>;

		reset-names = "pcie_0_core_reset",

					"pcie_phy_reset";

		qcom,aux-clk-freq = <0x14>;

		qcom,ep-latency = <10>;

		qcom,boot-option = <0x1>;

		qcom,pcie-phy-ver = <0x10>;

		qcom,phy-status-offset = <0x974>;

		qcom,phy-status-bit = <6>;

		qcom,phy-power-down-offset = <0x804>;

		qcom,phy-sequence = <0x800 0x01 0x0

				0x804 0x03 0x0

				0x034 0x18 0x0

				0x038 0x10 0x0

				0x294 0x06 0x0

				0x0c8 0x01 0x0

				0x128 0x00 0x0

				0x144 0xff 0x0

				0x148 0x1f 0x0

				0x070 0x0f 0x0

				0x048 0x0f 0x0

				0x178 0x00 0x0

				0x19c 0x01 0x0

				0x18c 0x20 0x0

				0x184 0x0a 0x0

				0x00c 0x09 0x0

				0x0ac 0x04 0x0

				0x0d0 0x82 0x0

				0x0e4 0x03 0x0

				0x0e0 0x55 0x0

				0x0dc 0x55 0x0

				0x054 0x00 0x0

				0x050 0x0d 0x0

				0x04c 0x04 0x0

				0x174 0x33 0x0

				0x03c 0x02 0x0

				0x040 0x1f 0x0

				0x078 0x0b 0x0

				0x084 0x16 0x0

				0x090 0x28 0x0

				0x10c 0x00 0x0

				0x108 0x80 0x0

				0x010 0x01 0x0

				0x01c 0x31 0x0

				0x020 0x01 0x0

				0x014 0x02 0x0

				0x018 0x00 0x0

				0x024 0x2f 0x0

				0x028 0x19 0x0

				0x268 0x45 0x0

				0x194 0x06 0x0

				0x254 0x02 0x0

				0x2ac 0x12 0x0

				0x510 0x1c 0x0

				0x51c 0x14 0x0

				0x4d8 0x01 0x0

				0x4dc 0x00 0x0

				0x4e0 0xdb 0x0

				0x448 0x4b 0x0

				0x41c 0x04 0x0

				0x410 0x04 0x0

				0x074 0x19 0x0

				0x854 0x04 0x0

				0x9ac 0x00 0x0

				0x8a0 0x40 0x0

				0x9e0 0x00 0x0

				0x9dc 0x40 0x0

				0x9a8 0x00 0x0

				0x8a4 0x40 0x0

				0x8a8 0x73 0x0

				0x518 0x99 0x0

				0x824 0x15 0x0

				0x828 0x0e 0x0

				0x9b0 0x07 0x0

				0x800 0x00 0x0

				0x808 0x03 0x0>;

		pcie0_rp: pcie0_rp {

			reg = <0 0 0 0 0>;

		};

	};

	pcie0_msi: qcom,pcie0_msi@a0000000 {

		compatible = "qcom,pci-msi";

		msi-controller;

		reg = <0xa0000000 0x0>;

		interrupt-parent = <&intc>;

		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

		qcom,snps;

	};

};

#include "sdxnightjar-coresight.dtsi"

#include "sdxnightjar-pinctrl.dtsi"

#include "sdxnightjar-blsp.dtsi"

#include "sdxnightjar-pcie.dtsi"

&i2c_3 {

	status = "ok";