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Commit 6f3fff60 authored by Deepak M's avatar Deepak M Committed by Jani Nikula
Browse files

drm/i915: Add ddb size field to device info structure 



Adding the ddb size into the devide info will avoid
platform checks while computing wm.

v2: Added comment and WARN_ON if ddb size is zero.(Jani)
v3: Added WARN_ON at the right place.(Jani)

Suggested-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: default avatarDeepak M <m.deepak@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1473931870-7724-1-git-send-email-m.deepak@intel.com
parent 7a9347f9

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -710,6 +710,7 @@ struct intel_device_info { 
	u8 ring_mask; /* Rings supported by the HW */

	u8 num_rings;

	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);

	u16 ddb_size; /* in blocks */

	/* Register offsets for the various display pipes and transcoders */

	int pipe_offsets[I915_MAX_TRANSCODERS];

	int trans_offsets[I915_MAX_TRANSCODERS];

drivers/gpu/drm/i915/i915_pci.c

+5 −0
Original line number Diff line number Diff line
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = { 
	.gen = 9,

	.has_csr = 1,

	.has_guc = 1,

	.ddb_size = 896,

};



static const struct intel_device_info intel_skylake_gt3_info = {
@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { 
	.gen = 9,

	.has_csr = 1,

	.has_guc = 1,

	.ddb_size = 896,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

};
@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = { 
	.has_hw_contexts = 1,

	.has_logical_ring_contexts = 1,

	.has_guc = 1,

	.ddb_size = 512,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

	BDW_COLORS,
@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = { 
	.gen = 9,

	.has_csr = 1,

	.has_guc = 1,

	.ddb_size = 896,

};



static const struct intel_device_info intel_kabylake_gt3_info = {
@@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = { 
	.gen = 9,

	.has_csr = 1,

	.has_guc = 1,

	.ddb_size = 896,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

};

drivers/gpu/drm/i915/intel_pm.c

+2 −11
Original line number Diff line number Diff line
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev) 
	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);

}



/*

 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the

 * different active planes.

 */



#define SKL_DDB_SIZE		896	/* in blocks */

#define BXT_DDB_SIZE		512

#define SKL_SAGV_BLOCK_TIME	30 /* µs */



/*
@@ -3057,10 +3050,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, 
	else

		*num_active = hweight32(dev_priv->active_crtcs);



	if (IS_BROXTON(dev))

		ddb_size = BXT_DDB_SIZE;

	else

		ddb_size = SKL_DDB_SIZE;

	ddb_size = INTEL_INFO(dev_priv)->ddb_size;

	WARN_ON(ddb_size == 0);



	ddb_size -= 4; /* 4 blocks for bypass path allocation */