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Commit 6f36f361 authored by shiwgupt's avatar shiwgupt
Browse files

ARM: dts: msm: Add CSIPHY/CCI nodes for blair 

Add support for CSIPHY/CCI for blair camera.

CRs-Fixed: 2954621
Change-Id: Ic1aca1f2f858dc3a802977e62154543e80b461a7
parent 251df031

blair-camera.dtsi

+322 −0
Original line number Diff line number Diff line
@@ -6,6 +6,328 @@ 
		status = "ok";

	};



	cam_csiphy0: qcom,csiphy0 {

		cell-index = <0>;

		compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";

		reg = <0x05C52000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0x52000>;

		interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "mipi-csi-vdd1",

			"mipi-csi-vdd2";

		gdscr-supply = <&gcc_camss_top_gdsc>;

		mipi-csi-vdd1-supply = <&L7A>;

		mipi-csi-vdd2-supply = <&L4A>;

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 880000 1200000>;

		rgltr-max-voltage = <0 1050000 1300000>;

		rgltr-load-current = <0 16200 9000>;

		clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,

			<&gcc GCC_CAMSS_CPHY_0_CLK>,

			<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>,

			<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy0_clk",

			"csi0phytimer_clk_src",

			"csi0phytimer_clk";

		src-clock-name = "csi0phytimer_clk_src";

		clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";

		clock-rates =

			<256000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<384000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy1: qcom,csiphy1 {

		cell-index = <1>;

		compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";

		reg = <0x05C54000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0x54000>;

		interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "mipi-csi-vdd1",

			"mipi-csi-vdd2";

		gdscr-supply = <&gcc_camss_top_gdsc>;

		mipi-csi-vdd1-supply = <&L7A>;

		mipi-csi-vdd2-supply = <&L4A>;

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 880000 1200000>;

		rgltr-max-voltage = <0 1050000 1300000>;

		rgltr-load-current = <0 16200 9000>;

		clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,

			<&gcc GCC_CAMSS_CPHY_1_CLK>,

			<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>,

			<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy1_clk",

			"csi1phytimer_clk_src",

			"csi1phytimer_clk";

		src-clock-name = "csi1phytimer_clk_src";

		clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";

		clock-rates =

			<256000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<384000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy2: qcom,csiphy2 {

		cell-index = <2>;

		compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";

		reg = <0x05C56000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0x56000>;

		interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "mipi-csi-vdd1",

			"mipi-csi-vdd2";

		gdscr-supply = <&gcc_camss_top_gdsc>;

		mipi-csi-vdd1-supply = <&L7A>;

		mipi-csi-vdd2-supply = <&L4A>;

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 880000 1200000>;

		rgltr-max-voltage = <0 1050000 1300000>;

		rgltr-load-current = <0 16200 9000>;

		clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,

			<&gcc GCC_CAMSS_CPHY_2_CLK>,

			<&gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>,

			<&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

				"csiphy2_clk",

				"csi2phytimer_clk_src",

				"csi2phytimer_clk";

		src-clock-name = "csi2phytimer_clk_src";

		clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";

		clock-rates =

			<256000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<384000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy3: qcom,csiphy3 {

		cell-index = <3>;

		compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";

		reg = <0x05C58000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0x58000>;

		interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "mipi-csi-vdd1",

			"mipi-csi-vdd2";

		gdscr-supply = <&gcc_camss_top_gdsc>;

		mipi-csi-vdd1-supply = <&L7A>;

		mipi-csi-vdd2-supply = <&L4A>;

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 880000 1200000>;

		rgltr-max-voltage = <0 1050000 1300000>;

		rgltr-load-current = <0 16200 9000>;

		clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,

			<&gcc GCC_CAMSS_CPHY_3_CLK>,

			<&gcc GCC_CAMSS_CSI3PHYTIMER_CLK_SRC>,

			<&gcc GCC_CAMSS_CSI3PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

				"csiphy3_clk",

				"csi3phytimer_clk_src",

				"csi3phytimer_clk";

		src-clock-name = "csi3phytimer_clk_src";

		clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";

		clock-rates =

			<256000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<384000000 0 300000000 0>;

		status = "ok";

	};



	cam_cci0: qcom,cci0 {

		cell-index = <0>;

		compatible = "qcom,cci", "simple-bus";

		reg = <0x05C1B000 0x1000>;

		reg-names = "cci";

		reg-cam-base = <0x1B000>;

		interrupt-names = "cci";

		interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;

		status = "ok";

		gdscr-supply = <&gcc_camss_top_gdsc>;

		regulator-names = "gdscr";

		clocks = <&gcc GCC_CAMSS_CCI_0_CLK>,

			<&gcc GCC_CAMSS_CCI_0_CLK_SRC>;

		clock-names = "cci_0_clk",

				"cci_0_clk_src";

		src-clock-name = "cci_0_clk_src";

		clock-cntl-level = "svs";

		clock-rates = <0 37500000>;

		pinctrl-names = "cam_default", "cam_suspend";

		pinctrl-0 = <&cci0_active &cci1_active>;

		pinctrl-1 = <&cci0_suspend &cci1_suspend>;

		gpios = <&tlmm 39 0>,

			<&tlmm 40 0>,

			<&tlmm 41 0>,

			<&tlmm 42 0>;

		gpio-req-tbl-num = <0 1 2 3>;

		gpio-req-tbl-flags = <1 1 1 1>;

		gpio-req-tbl-label = "CCI_I2C_DATA0",

			"CCI_I2C_CLK0",

			"CCI_I2C_DATA1",

			"CCI_I2C_CLK1";



		i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {

			hw-thigh = <201>;

			hw-tlow = <174>;

			hw-tsu-sto = <204>;

			hw-tsu-sta = <231>;

			hw-thd-dat = <22>;

			hw-thd-sta = <162>;

			hw-tbuf = <227>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_custom_cci0: qcom,i2c_custom_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <1>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {

			hw-thigh = <16>;

			hw-tlow = <22>;

			hw-tsu-sto = <17>;

			hw-tsu-sta = <18>;

			hw-thd-dat = <16>;

			hw-thd-sta = <15>;

			hw-tbuf = <24>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <3>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};

	};



	cam_cci1: qcom,cci1 {

		cell-index = <1>;

		compatible = "qcom,cci", "simple-bus";

		reg = <0x05C1C000 0x1000>;

		reg-names = "cci";

		reg-cam-base = <0x1C000>;

		interrupt-names = "cci";

		interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;

		status = "ok";

		gdscr-supply = <&gcc_camss_top_gdsc>;

		regulator-names = "gdscr";

		clocks = <&gcc GCC_CAMSS_CCI_1_CLK>,

			<&gcc GCC_CAMSS_CCI_1_CLK_SRC>;

		clock-names = "cci_1_clk",

				"cci_1_clk_src";

		src-clock-name = "cci_1_clk_src";

		clock-cntl-level = "svs";

		clock-rates = <0 37500000>;

		pinctrl-names = "cam_default", "cam_suspend";

		pinctrl-0 = <&cci2_active>;

		pinctrl-1 = <&cci2_suspend>;

		gpios = <&tlmm 43 0>,

			<&tlmm 44 0>;

		gpio-req-tbl-num = <0 1>;

		gpio-req-tbl-flags = <1 1>;

		gpio-req-tbl-label = "CCI_I2C_DATA2",

			"CCI_I2C_CLK2";



		i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {

			hw-thigh = <201>;

			hw-tlow = <174>;

			hw-tsu-sto = <204>;

			hw-tsu-sta = <231>;

			hw-thd-dat = <22>;

			hw-thd-sta = <162>;

			hw-tbuf = <227>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_custom_cci1: qcom,i2c_custom_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <1>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {

			hw-thigh = <16>;

			hw-tlow = <22>;

			hw-tsu-sto = <17>;

			hw-tsu-sta = <18>;

			hw-thd-dat = <16>;

			hw-thd-sta = <15>;

			hw-tbuf = <24>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <3>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};

	};



	qcom,cam-sync {

		compatible = "qcom,cam-sync";

		status = "ok";