Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6f2f48a9 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms/evergreen: flush hdp cache when flushing gart tlb 



Make sure vram changes hit memory.  This mirrors the
6xx/7xx behavior.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent a1a82133

drivers/gpu/drm/radeon/evergreen.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -748,6 +748,8 @@ void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) 
	unsigned i;

	unsigned i;

	u32 tmp;

	u32 tmp;





	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);



	WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));

	WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));

	for (i = 0; i < rdev->usec_timeout; i++) {

	for (i = 0; i < rdev->usec_timeout; i++) {

		/* read MC_STATUS */

		/* read MC_STATUS */

drivers/gpu/drm/radeon/evergreend.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -174,6 +174,7 @@ 
#define	HDP_NONSURFACE_BASE				0x2C04

#define	HDP_NONSURFACE_BASE				0x2C04

#define	HDP_NONSURFACE_INFO				0x2C08

#define	HDP_NONSURFACE_INFO				0x2C08

#define	HDP_NONSURFACE_SIZE				0x2C0C

#define	HDP_NONSURFACE_SIZE				0x2C0C

#define HDP_MEM_COHERENCY_FLUSH_CNTL			0x5480

#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0

#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0

#define	HDP_TILING_CONFIG				0x2F3C

#define	HDP_TILING_CONFIG				0x2F3C