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Commit 6f2185f8 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux into arm/drivers 

Reset controller changes for v5.1

This adds the include/linux/reset directory to MAINTAINERS for reset
specific headers and adds headers for sunxi and socfpga in there to
get rid of a few extern function declarations.
There is a new reset driver for the Broadcom STB reset controller and
the i.MX7 system reset controller driver is extended to support i.MX8MQ
as well. Finally, there is a new header with reset id constants for
the Meson G12A SoC, which has a reset controller identical to Meson AXG
and thus can reuse its driver and DT bindings.

* tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux

:
  dt-bindings: reset: meson: add g12a bindings
  reset: imx7: Add support for i.MX8MQ IP block variant
  reset: imx7: Add plubming to support multiple IP variants
  reset: Add Broadcom STB SW_INIT reset controller driver
  dt-bindings: reset: Add document for Broadcom STB reset controller
  reset: socfpga: declare socfpga_reset_init in a header file
  reset: sunxi: declare sun6i_reset_init in a header file
  MAINTAINERS: use include/linux/reset for reset controller related headers
  dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 1d03f187 dbfc5453

Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt

0 → 100644
+27 −0
Original line number Diff line number Diff line 
Broadcom STB SW_INIT-style reset controller

===========================================



Broadcom STB SoCs have a SW_INIT-style reset controller with separate

SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit

reset lines.



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: should be brcm,brcmstb-reset

- reg: register base and length

- #reset-cells: must be set to 1



Example:



	reset: reset-controller@8404318 {

		compatible = "brcm,brcmstb-reset";

		reg = <0x8404318 0x30>;

		#reset-cells = <1>;

	};



	&ethernet_switch {

		resets = <&reset>;

		reset-names = "switch";

	};

Documentation/devicetree/bindings/reset/fsl,imx7-src.txt

+5 −2
Original line number Diff line number Diff line
@@ -5,7 +5,9 @@ Please also refer to reset.txt in this directory for common reset 
controller binding usage.



Required properties:

- compatible: Should be "fsl,imx7d-src", "syscon"

- compatible:

	- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"

	- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain SRC interrupt
@@ -44,4 +46,5 @@ Example: 




For list of all valid reset indicies see

<dt-bindings/reset/imx7-reset.h>
 
<dt-bindings/reset/imx7-reset.h> for i.MX7 and

<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -12958,6 +12958,7 @@ F: drivers/reset/ 
F:	Documentation/devicetree/bindings/reset/

F:	include/dt-bindings/reset/

F:	include/linux/reset.h

F:	include/linux/reset/

F:	include/linux/reset-controller.h



RESTARTABLE SEQUENCES SUPPORT

arch/arm/mach-socfpga/socfpga.c

+1 −2
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#include <linux/of_irq.h>

#include <linux/of_platform.h>

#include <linux/reboot.h>

#include <linux/reset/socfpga.h>



#include <asm/hardware/cache-l2x0.h>

#include <asm/mach/arch.h>
@@ -32,8 +33,6 @@ void __iomem *rst_manager_base_addr; 
void __iomem *sdr_ctl_base_addr;

unsigned long socfpga_cpu1start_addr;



extern void __init socfpga_reset_init(void);



static void __init socfpga_sysmgr_init(void)

{

	struct device_node *np;

arch/arm/mach-sunxi/sunxi.c

+1 −1
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <linux/clocksource.h>

#include <linux/init.h>

#include <linux/platform_device.h>

#include <linux/reset/sunxi.h>



#include <asm/mach/arch.h>

#include <asm/secure_cntvoff.h>
@@ -37,7 +38,6 @@ static const char * const sun6i_board_dt_compat[] = { 
	NULL,

};



extern void __init sun6i_reset_init(void);

static void __init sun6i_timer_init(void)

{

	of_clk_init(NULL);