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Commit 6ee2846c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2019-02-22' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "This contains a single i915 tiled display fix, and a set of
  amdgpu/radeon fixes.

  i915:

   - tiled display fix

  amdgpu/radeon:

   - runtime PM fix

   - bulk moves disable (fix is too large for 5.0)

   - a set of display fixes that are all cc'ed stable so we didn't want
     to leave them until -next"

* tag 'drm-fixes-2019-02-22' of git://anongit.freedesktop.org/drm/drm:
  drm/amdgpu: disable bulk moves for now
  drm/amd/display: set clocks to 0 on suspend on dce80
  drm/amd/display: fix optimize_bandwidth func pointer for dce80
  drm/amd/display: Fix negative cursor pos programming
  drm/i915/fbdev: Actually configure untiled displays
  drm/amd/display: Raise dispclk value for dce11
  drm/amd/display: Fix MST reboot/poweroff sequence
  drm/amdgpu: Update sdma golden setting for vega20
  drm/amdgpu: Set DPM_FLAG_NEVER_SKIP when enabling PM-runtime
  gpu: drm: radeon: Set DPM_FLAG_NEVER_SKIP when enabling PM-runtime
parents 168bd298 019276ed

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+1 −0
Original line number Diff line number Diff line
@@ -212,6 +212,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 
	}



	if (amdgpu_device_is_px(dev)) {

		dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);

		pm_runtime_use_autosuspend(dev->dev);

		pm_runtime_set_autosuspend_delay(dev->dev, 5000);

		pm_runtime_set_active(dev->dev);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+2 −0
Original line number Diff line number Diff line
@@ -638,12 +638,14 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 
	struct ttm_bo_global *glob = adev->mman.bdev.glob;

	struct amdgpu_vm_bo_base *bo_base;



#if 0

	if (vm->bulk_moveable) {

		spin_lock(&glob->lru_lock);

		ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);

		spin_unlock(&glob->lru_lock);

		return;

	}

#endif



	memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+2 −2
Original line number Diff line number Diff line
@@ -128,7 +128,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 


static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =

{

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
@@ -158,7 +158,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 
};



static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+3 −2
Original line number Diff line number Diff line
@@ -786,12 +786,13 @@ static int dm_suspend(void *handle) 
	struct amdgpu_display_manager *dm = &adev->dm;

	int ret = 0;



	WARN_ON(adev->dm.cached_state);

	adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);



	s3_handle_mst(adev->ddev, true);



	amdgpu_dm_irq_suspend(adev);



	WARN_ON(adev->dm.cached_state);

	adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);



	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

+8 −3
Original line number Diff line number Diff line
@@ -662,6 +662,11 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr, 
{

	struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);

	struct dm_pp_power_level_change_request level_change_req;

	int patched_disp_clk = context->bw.dce.dispclk_khz;



	/*TODO: W/A for dal3 linux, investigate why this works */

	if (!clk_mgr_dce->dfs_bypass_active)

		patched_disp_clk = patched_disp_clk * 115 / 100;



	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);

	/* get max clock state from PPLIB */
@@ -671,9 +676,9 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr, 
			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;

	}



	if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {

		context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, context->bw.dce.dispclk_khz);

		clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;

	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {

		context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk);

		clk_mgr->clks.dispclk_khz = patched_disp_clk;

	}

	dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);

}