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Commit 6edafc4e authored by José Roberto de Souza's avatar José Roberto de Souza Committed by Rodrigo Vivi
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drm/i915: Unset reset pch handshake when PCH is not present in one place 



Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
i915_gem_init_hw().
So making skl_pch_reset_handshake() handle both cases and calling
it for the missing gens in intel_power_domains_init_hw().
Ivybridge have a different register and bits but with the same
objective so moving it too.

v2(Rodrigo):
- handling IVYBRIDGE case inside intel_pch_reset_handshake()

v4(Rodrigo and Ville):
- moving the enable/disable decision to callers

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180918204714.27306-2-jose.souza@intel.com
parent 7c86828d

drivers/gpu/drm/i915/i915_gem.c

+0 −12
Original line number Diff line number Diff line
@@ -5301,18 +5301,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) 
		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?

			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);



	if (HAS_PCH_NOP(dev_priv)) {

		if (IS_IVYBRIDGE(dev_priv)) {

			u32 temp = I915_READ(GEN7_MSG_CTL);

			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);

			I915_WRITE(GEN7_MSG_CTL, temp);

		} else if (INTEL_GEN(dev_priv) >= 7) {

			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);

			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;

			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);

		}

	}



	intel_gt_workarounds_apply(dev_priv);



	i915_gem_init_swizzling(dev_priv);

drivers/gpu/drm/i915/intel_runtime_pm.c

+20 −8
Original line number Diff line number Diff line
@@ -3243,14 +3243,25 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) 
static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,

				      bool enable)

{

	u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);

	i915_reg_t reg;

	u32 reset_bits, val;



	if (IS_IVYBRIDGE(dev_priv)) {

		reg = GEN7_MSG_CTL;

		reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;

	} else {

		reg = HSW_NDE_RSTWRN_OPT;

		reset_bits = RESET_PCH_HANDSHAKE_ENABLE;

	}



	val = I915_READ(reg);



	if (enable)

		val |= RESET_PCH_HANDSHAKE_ENABLE;

		val |= reset_bits;

	else

		val &= ~RESET_PCH_HANDSHAKE_ENABLE;

		val &= ~reset_bits;



	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);

	I915_WRITE(reg, val);

}



static void skl_display_core_init(struct drm_i915_private *dev_priv,
@@ -3262,7 +3273,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, 
	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);



	/* enable PCH reset handshake */

	intel_pch_reset_handshake(dev_priv, true);

	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));



	/* enable PG1 and Misc I/O */

	mutex_lock(&power_domains->lock);
@@ -3448,7 +3459,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume 
	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);



	/* 1. Enable PCH Reset Handshake */

	intel_pch_reset_handshake(dev_priv, true);

	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));



	/* 2. Enable Comp */

	val = I915_READ(CHICKEN_MISC_2);
@@ -3531,7 +3542,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, 
	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);



	/* 1. Enable PCH reset handshake. */

	intel_pch_reset_handshake(dev_priv, true);

	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));



	for (port = PORT_A; port <= PORT_B; port++) {

		/* 2. Enable DDI combo PHY comp. */
@@ -3763,7 +3774,8 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 
		mutex_lock(&power_domains->lock);

		vlv_cmnlane_wa(dev_priv);

		mutex_unlock(&power_domains->lock);

	}

	} else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)

		intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));



	/*

	 * Keep all power wells enabled for any dependent HW access during