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Commit 6ead7e48 authored by Dave Jiang's avatar Dave Jiang Committed by Vinod Koul
Browse files

ioatdma: skip legacy reset bits since v3.3 plattform doesn't need it 



Make it so only 3.2 and earlier platform need the PCI config register
clearings since this implementation does not have the registers.

Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Acked-by: default avatarDan Williams <djbw@fb.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent 8a52b9ff

drivers/dma/ioat/dma_v3.c

+21 −13
Original line number Diff line number Diff line
@@ -1331,20 +1331,28 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan) 
	chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);

	writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);



	if (device->version < IOAT_VER_3_3) {

		/* clear any pending errors */

	err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);

		err = pci_read_config_dword(pdev,

				IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);

		if (err) {

		dev_err(&pdev->dev, "channel error register unreachable\n");

			dev_err(&pdev->dev,

				"channel error register unreachable\n");

			return err;

		}

	pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr);

		pci_write_config_dword(pdev,

				IOAT_PCI_CHANERR_INT_OFFSET, chanerr);



		/* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit

		 * (workaround for spurious config parity error after restart)

		 */

		pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);

	if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0)

		pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10);

		if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {

			pci_write_config_dword(pdev,

					       IOAT_PCI_DMAUNCERRSTS_OFFSET,

					       0x10);

		}

	}



	err = ioat2_reset_sync(chan, msecs_to_jiffies(200));

	if (err) {