Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6deef9b6 authored by Vidya Srinivas's avatar Vidya Srinivas Committed by Maarten Lankhorst
Browse files

drm/i915: Enable Display WA 0528 



Possible hang with NV12 plane surface formats.
WA: When the plane source pixel format is NV12,
the CHICKEN_PIPESL_* register bit 22 must be set to 1
and the render decompression must not be enabled
on any of the planes in that pipe.

v2: removed unnecessary POSTING_READ

v3: Added RB from Maarten

v4: Removed support for NV12 for BROXTON

Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: default avatarVidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1526074397-10457-3-git-send-email-vidya.srinivas@intel.com
parent 8e021151

drivers/gpu/drm/i915/intel_display.c

+19 −3
Original line number Diff line number Diff line
@@ -488,10 +488,22 @@ static const struct intel_limit intel_limits_bxt = { 
	.p2 = { .p2_slow = 1, .p2_fast = 20 },

};



static void

skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)

{

	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))

		return;



	if (enable)

		I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);

	else

		I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);

}



static void

skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)

{

	if (IS_SKYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))

		return;



	if (enable)
@@ -5193,8 +5205,10 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) 


	/* Display WA 827 */

	if (needs_nv12_wa(dev_priv, old_crtc_state) &&

	    !needs_nv12_wa(dev_priv, pipe_config))

	    !needs_nv12_wa(dev_priv, pipe_config)) {

		skl_wa_clkgate(dev_priv, crtc->pipe, false);

		skl_wa_528(dev_priv, crtc->pipe, false);

	}

}



static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
@@ -5231,8 +5245,10 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, 


	/* Display WA 827 */

	if (!needs_nv12_wa(dev_priv, old_crtc_state) &&

	    needs_nv12_wa(dev_priv, pipe_config))

	    needs_nv12_wa(dev_priv, pipe_config)) {

		skl_wa_clkgate(dev_priv, crtc->pipe, true);

		skl_wa_528(dev_priv, crtc->pipe, true);

	}



	/*

	 * Vblank time updates from the shadow to live plane control register