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Commit 6de20237 authored by Eric Yang's avatar Eric Yang Committed by Alex Deucher
Browse files

drm/amd/display: move bw calc code into helpers 



[Why]
For better readability and reusability

[How]
Move snippets of BW calculation code into helpers.

Signed-off-by: default avatarEric Yang <Eric.Yang2@amd.com>
Reviewed-by: default avatarFatemeh Darbehani <Fatemeh.Darbehani@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4bc84690

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

+0 −2
Original line number Diff line number Diff line
@@ -26,8 +26,6 @@ 
#include "dccg.h"

#include "clk_mgr_internal.h"





#include "dcn20/dcn20_clk_mgr.h"

#include "dce100/dce_clk_mgr.h"

#include "reg_helper.h"

#include "core_types.h"

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+153 −97
Original line number Diff line number Diff line
@@ -2018,15 +2018,16 @@ static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 
}

#endif



bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

		bool fast_validate)

bool dcn20_fast_validate_bw(

		struct dc *dc,

		struct dc_state *context,

		display_e2e_pipe_params_st *pipes,

		int *pipe_split_from,

		int *vlevel_out)

{

	bool out = false;



	BW_VAL_TRACE_SETUP();



	int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;

	int pipe_split_from[MAX_PIPES];

	bool odm_capable = context->bw_ctx.dml.ip.odm_capable;

	bool force_split = false;

#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
@@ -2034,10 +2035,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
#endif

	int split_threshold = dc->res_pool->pipe_count / 2;

	bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;

	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);

	DC_LOGGER_INIT(dc->ctx->logger);



	BW_VAL_TRACE_COUNT();



	ASSERT(pipes);

	if (!pipes)
@@ -2077,7 +2075,6 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
			&context->res_ctx, pipes);



	if (!pipe_cnt) {

		BW_VAL_TRACE_SKIP(pass);

		out = true;

		goto validate_out;

	}
@@ -2242,14 +2239,27 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
	}

#endif



	BW_VAL_TRACE_END_VOLTAGE_LEVEL();

	*vlevel_out = vlevel;



	if (fast_validate) {

		BW_VAL_TRACE_SKIP(fast);

	out = true;

	goto validate_out;



validate_fail:

	out = false;



validate_out:

	return out;

}



void dcn20_calculate_wm(

		struct dc *dc, struct dc_state *context,

		display_e2e_pipe_params_st *pipes,

		int *out_pipe_cnt,

		int *pipe_split_from,

		int vlevel)

{

	int pipe_cnt, i, pipe_idx;



	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

			if (!context->res_ctx.pipe_ctx[i].stream)

				continue;
@@ -2275,10 +2285,12 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
				else

					pipes[pipe_cnt].pipe.dest.odm_combine = 0;

			}



			if (dc->config.forced_clocks) {

				pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;

				pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;

			}



			pipe_cnt++;

		}
@@ -2291,6 +2303,8 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
					&context->res_ctx, pipes);

		}



		*out_pipe_cnt = pipe_cnt;



		pipes[0].clks_cfg.voltage = vlevel;

		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;

		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
@@ -2337,6 +2351,16 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

		context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

}



void dcn20_calculate_dlg_params(

		struct dc *dc, struct dc_state *context,

		display_e2e_pipe_params_st *pipes,

		int pipe_cnt,

		int vlevel)

{

	int i, pipe_idx;



	/* Writeback MCIF_WB arbitration parameters */

	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
@@ -2351,7 +2375,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
							!= dm_dram_clock_change_unsupported;

	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;



	BW_VAL_TRACE_END_WATERMARKS();





	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)
@@ -2393,8 +2417,40 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
				pipes[pipe_idx].pipe);

		pipe_idx++;

	}

}



bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

		bool fast_validate)

{

	bool out = false;



	BW_VAL_TRACE_SETUP();



	int vlevel = 0;

	int pipe_split_from[MAX_PIPES];

	int pipe_cnt = 0;

	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);

	DC_LOGGER_INIT(dc->ctx->logger);



	BW_VAL_TRACE_COUNT();



	out = dcn20_fast_validate_bw(dc, context, pipes, pipe_split_from, &vlevel);



	if (!out)

		goto validate_fail;



	BW_VAL_TRACE_END_VOLTAGE_LEVEL();



	if (fast_validate) {

		BW_VAL_TRACE_SKIP(fast);

		goto validate_out;

	}



	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);

	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);



	BW_VAL_TRACE_END_WATERMARKS();



	out = true;

	goto validate_out;



validate_fail:

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h

+11 −0
Original line number Diff line number Diff line
@@ -116,6 +116,17 @@ void dcn20_set_mcif_arb_params( 
		display_e2e_pipe_params_st *pipes,

		int pipe_cnt);

bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);

bool dcn20_fast_validate_bw(

		struct dc *dc,

		struct dc_state *context,

		display_e2e_pipe_params_st *pipes,

		int *pipe_split_from,

		int *vlevel_out);

void dcn20_calculate_dlg_params(

		struct dc *dc, struct dc_state *context,

		display_e2e_pipe_params_st *pipes,

		int pipe_cnt,

		int vlevel);



enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

+2 −0
Original line number Diff line number Diff line
@@ -64,6 +64,8 @@ enum dentist_divider_range { 
 ***************************************************************************************

 */



/* Macros */



#define TO_CLK_MGR_INTERNAL(clk_mgr)\

	container_of(clk_mgr, struct clk_mgr_internal, base)