Unverified Commit 6db170ff authored Oct 02, 2018 by Atish Patra Committed by Palmer Dabbelt Oct 22, 2018

RISC-V: Disable preemption before enabling interrupts



Currently, irq is enabled before preemption disabling happens.
If the scheduler fired right here and cpu is scheduled then it
may blow up.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
[Atish: Commit text and code comment formatting update]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

parent b18d6f05

arch/riscv/kernel/smpboot.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -111,7 +111,11 @@ asmlinkage void __init smp_callin(void)
		* a local TLB flush right now just in case.
		*/
		local_flush_tlb_all();
		local_irq_enable();
		/*
		* Disable preemption before enabling interrupts, so we don't try to
		* schedule a CPU that hasn't actually started yet.
		*/
		preempt_disable();
		local_irq_enable();
		cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
		}