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Commit 6d4cf750 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Andy Gross
Browse files

arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP 



Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files

Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent f3b2c99e

arch/arm64/boot/dts/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb 
dtb-$(CONFIG_ARCH_QCOM)	+= msm8992-bullhead-rev-101.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-angler-rev-101.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-mtp.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-mtp.dtb

arch/arm64/boot/dts/qcom/sdm845-mtp.dts

0 → 100644
+15 −0
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// SPDX-License-Identifier: GPL-2.0

/*

 * SDM845 MTP board device tree source

 *

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 */



/dts-v1/;



#include "sdm845.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. SDM845 MTP";

	compatible = "qcom,sdm845-mtp";

};

arch/arm64/boot/dts/qcom/sdm845.dtsi

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+276 −0
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// SPDX-License-Identifier: GPL-2.0

/*

 * SDM845 SoC device tree source

 *

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	interrupt-parent = <&intc>;



	#address-cells = <2>;

	#size-cells = <2>;



	chosen { };



	memory@80000000 {

		device_type = "memory";

		/* We expect the bootloader to fill in the size */

		reg = <0 0x80000000 0 0>;

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

				L3_0: l3-cache {

				      compatible = "cache";

				};

			};

		};



		CPU1: cpu@100 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&L2_100>;

			L2_100: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU2: cpu@200 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x200>;

			enable-method = "psci";

			next-level-cache = <&L2_200>;

			L2_200: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU3: cpu@300 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x300>;

			enable-method = "psci";

			next-level-cache = <&L2_300>;

			L2_300: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU4: cpu@400 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x400>;

			enable-method = "psci";

			next-level-cache = <&L2_400>;

			L2_400: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU5: cpu@500 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x500>;

			enable-method = "psci";

			next-level-cache = <&L2_500>;

			L2_500: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU6: cpu@600 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x600>;

			enable-method = "psci";

			next-level-cache = <&L2_600>;

			L2_600: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU7: cpu@700 {

			device_type = "cpu";

			compatible = "qcom,kryo385";

			reg = <0x0 0x700>;

			enable-method = "psci";

			next-level-cache = <&L2_700>;

			L2_700: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;

	};



	clocks {

		xo_board: xo-board {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <19200000>;

		};



		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32764>;

		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	soc: soc {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0 0xffffffff>;

		compatible = "simple-bus";



		intc: interrupt-controller@17a00000 {

			compatible = "arm,gic-v3";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			#interrupt-cells = <3>;

			interrupt-controller;

			reg = <0x17a00000 0x10000>,     /* GICD */

			      <0x17a60000 0x100000>;    /* GICR * 8 */

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;



			gic-its@17a40000 {

				compatible = "arm,gic-v3-its";

				msi-controller;

				#msi-cells = <1>;

				reg = <0x17a40000 0x20000>;

				status = "disabled";

			};

		};



		gcc: clock-controller@100000 {

			compatible = "qcom,gcc-sdm845";

			reg = <0x100000 0x1f0000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		tlmm: pinctrl@3400000 {

			compatible = "qcom,sdm845-pinctrl";

			reg = <0x03400000 0xc00000>;

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		timer@17c90000 {

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			compatible = "arm,armv7-timer-mem";

			reg = <0x17c90000 0x1000>;



			frame@17ca0000 {

				frame-number = <0>;

				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x17ca0000 0x1000>,

				      <0x17cb0000 0x1000>;

			};



			frame@17cc0000 {

				frame-number = <1>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x17cc0000 0x1000>;

				status = "disabled";

			};



			frame@17cd0000 {

				frame-number = <2>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x17cd0000 0x1000>;

				status = "disabled";

			};



			frame@17ce0000 {

				frame-number = <3>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x17ce0000 0x1000>;

				status = "disabled";

			};



			frame@17cf0000 {

				frame-number = <4>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x17cf0000 0x1000>;

				status = "disabled";

			};



			frame@17d00000 {

				frame-number = <5>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x17d00000 0x1000>;

				status = "disabled";

			};



			frame@17d10000 {

				frame-number = <6>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x17d10000 0x1000>;

				status = "disabled";

			};

		};



		spmi_bus: spmi@c440000 {

			compatible = "qcom,spmi-pmic-arb";

			reg = <0xc440000 0x1100>,

			      <0xc600000 0x2000000>,

			      <0xe600000 0x100000>,

			      <0xe700000 0xa0000>,

			      <0xc40a000 0x26000>;

			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";

			interrupt-names = "periph_irq";

			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;

			qcom,ee = <0>;

			qcom,channel = <0>;

			#address-cells = <2>;

			#size-cells = <0>;

			interrupt-controller;

			#interrupt-cells = <4>;

			cell-index = <0>;

		};

	};

};